/**************************************************************/
/*    Verilog module of datapath cell DPZDT001H               */
/*    Designed by    Lin Yang    VLSI Technology  Oct. 20, 90 */
/*    Designed by    Linda J. Xu      Compass     Feb. 11, 93 */
/*                                                            */
/*    The following is the port description                   */
/*    Data ports                                              */
/*        A    : the input port                               */
/*    Control ports                                           */
/*        INST_Z  : the zero detect flag                      */
/*    Parameters                                              */
/*        WORDSIZE  : the word size of the datapath cell      */
/*        DELAY     : the delay time from input to output     */
/*        BF        : the  with/without buffer flag           */
/*                    0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpzdt001h(A, INST_Z);

  parameter WORDSIZE = 8, DELAY = 5, BF = 1;
  input  [WORDSIZE-1:0] A;
  output INST_Z;

  reg  odd;

  function zdt;
    input [WORDSIZE-1:0] X;

    begin
      odd = WORDSIZE;
      case (|X)
            'b1:  zdt = 'b 0;
            'b0:  zdt = 'b 1;
            default zdt = 'b x;
      endcase
    end

  endfunction

  assign #DELAY INST_Z = ((BF == 0) & (!odd)) ?
                         ~zdt(A): zdt(A);

endmodule