tmem.v
16.4 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
// version: 0.0.5 date 8.sep.1994 series sgi_custom/uc1 voltage 3.3v
// mem: tmem: 256words*16bits: byte write enable
//
// copyright (c) nec corporation 1994
//
// for logic only verilog
// ^^^^^^^^^^
//
`define functional
`timescale 10ps / 10ps //1unit = 0.01ns
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module tmem (
pcg, // in clock input be
csb, // in chip select
web, // in write enable [h]
a, // in address input
di, // in data input
dout // oz data output
);
/****************************************************************/
/* parameter //// define bit and address pin number */
/* bit_num = 16, // number of databit */
/* adr_num = 8; // number of address */
/****************************************************************/
input [15:0] di;
input [7:0] a ;
input [1:0] web ;
input csb, pcg ;
output [15:0] dout;
wire [15:0] di;
wire [7:0] a ;
wire [1:0] web ;
wire [15:0] dout;
wire [15:8] _dih ;
wire [15:8] _dihn ;
wire [7:0] _dil ;
wire [7:0] _diln ;
wire [7:0] _a ;
wire [7:0] _an ;
wire [15:8] qdoh;
wire [7:0] qdol;
reg [15:8] qqdoh;
reg [7:0] qqdol;
wire [15:8] r_doh, w_doh;
wire [7:0] r_dol, w_dol;
wire n_writeh, n_writel, n_readh, n_readl;
// oen, n_portd;
reg we_regh, we_regl,
notif_wh, notif_rh,
notif_wl, notif_rl, notif_c;
/****************************************************************/
parameter
td = 100; // do hold , tpd when read , when write
`ifdef functional
`else
specify specparam
// thz = 150, // do "lh" -> "z" from csb
// tlz = 150, // do "z" -> "lh" from csb
tpc = 600, // clk "h" width ( precharge )
tev = 600, // clk "l" width
tas = 400, // address setup to pcg(negedge)
tah = 0, // address hold to pcg(posedge)
tws = 200, // web setup to pcg(negedge)
twh = 0, // web hold to pcg(posedge)
tds = 400, // di setup to pcg(posedge)
tdh = 0, // di hold to pcg(posedge)
tcs = 100, // csb setup to pcg(posedge)
tch = 0; // csb hold to pcg(negedge)
/****************************************************************/
// (csb *> do0) = ( 0, 0, thz, tlz, thz, tlz );
// (csb *> do1) = ( 0, 0, thz, tlz, thz, tlz );
// (csb *> do2) = ( 0, 0, thz, tlz, thz, tlz );
// (csb *> do3) = ( 0, 0, thz, tlz, thz, tlz );
// (csb *> do4) = ( 0, 0, thz, tlz, thz, tlz );
// (csb *> do5) = ( 0, 0, thz, tlz, thz, tlz );
// (csb *> do6) = ( 0, 0, thz, tlz, thz, tlz );
// (csb *> do7) = ( 0, 0, thz, tlz, thz, tlz );
$width( posedge pcg, tpc );
$width( negedge pcg, tev );
$setup( a[0], negedge pcg &&& n_writeh, tas, notif_wh);
$setup( a[0], negedge pcg &&& n_writel, tas, notif_wl);
$setup( a[1], negedge pcg &&& n_writeh, tas, notif_wh);
$setup( a[1], negedge pcg &&& n_writel, tas, notif_wl);
$setup( a[2], negedge pcg &&& n_writeh, tas, notif_wh);
$setup( a[2], negedge pcg &&& n_writel, tas, notif_wl);
$setup( a[3], negedge pcg &&& n_writeh, tas, notif_wh);
$setup( a[3], negedge pcg &&& n_writel, tas, notif_wl);
$setup( a[4], negedge pcg &&& n_writeh, tas, notif_wh);
$setup( a[4], negedge pcg &&& n_writel, tas, notif_wl);
$setup( a[5], negedge pcg &&& n_writeh, tas, notif_wh);
$setup( a[5], negedge pcg &&& n_writel, tas, notif_wl);
$setup( a[6], negedge pcg &&& n_writeh, tas, notif_wh);
$setup( a[6], negedge pcg &&& n_writel, tas, notif_wl);
$setup( a[7], negedge pcg &&& n_writeh, tas, notif_wh);
$setup( a[7], negedge pcg &&& n_writel, tas, notif_wl);
$setup( a[0], negedge pcg &&& n_readh, tas, notif_rh);
$setup( a[0], negedge pcg &&& n_readl, tas, notif_rl);
$setup( a[1], negedge pcg &&& n_readh, tas, notif_rh);
$setup( a[1], negedge pcg &&& n_readl, tas, notif_rl);
$setup( a[2], negedge pcg &&& n_readh, tas, notif_rh);
$setup( a[2], negedge pcg &&& n_readl, tas, notif_rl);
$setup( a[3], negedge pcg &&& n_readh, tas, notif_rh);
$setup( a[3], negedge pcg &&& n_readl, tas, notif_rl);
$setup( a[4], negedge pcg &&& n_readh, tas, notif_rh);
$setup( a[4], negedge pcg &&& n_readl, tas, notif_rl);
$setup( a[5], negedge pcg &&& n_readh, tas, notif_rh);
$setup( a[5], negedge pcg &&& n_readl, tas, notif_rl);
$setup( a[6], negedge pcg &&& n_readh, tas, notif_rh);
$setup( a[6], negedge pcg &&& n_readl, tas, notif_rl);
$setup( a[7], negedge pcg &&& n_readh, tas, notif_rh);
$setup( a[7], negedge pcg &&& n_readl, tas, notif_rl);
$setup( web[1], negedge pcg &&& n_writeh, tws, notif_wh);
$setup( web[0], negedge pcg &&& n_writel, tws, notif_wl);
$setup( web[1], negedge pcg &&& n_readh, tws, notif_rh);
$setup( web[0], negedge pcg &&& n_readl, tws, notif_rl);
$setup( di[0], posedge pcg &&& n_writel, tds, notif_wl);
$setup( di[1], posedge pcg &&& n_writel, tds, notif_wl);
$setup( di[2], posedge pcg &&& n_writel, tds, notif_wl);
$setup( di[3], posedge pcg &&& n_writel, tds, notif_wl);
$setup( di[4], posedge pcg &&& n_writel, tds, notif_wl);
$setup( di[5], posedge pcg &&& n_writel, tds, notif_wl);
$setup( di[6], posedge pcg &&& n_writel, tds, notif_wl);
$setup( di[7], posedge pcg &&& n_writel, tds, notif_wl);
$setup( di[8], posedge pcg &&& n_writeh, tds, notif_wh);
$setup( di[9], posedge pcg &&& n_writeh, tds, notif_wh);
$setup( di[10], posedge pcg &&& n_writeh, tds, notif_wh);
$setup( di[11], posedge pcg &&& n_writeh, tds, notif_wh);
$setup( di[12], posedge pcg &&& n_writeh, tds, notif_wh);
$setup( di[13], posedge pcg &&& n_writeh, tds, notif_wh);
$setup( di[14], posedge pcg &&& n_writeh, tds, notif_wh);
$setup( di[15], posedge pcg &&& n_writeh, tds, notif_wh);
$setup( csb, negedge pcg , tcs, notif_c);
$hold ( posedge pcg &&& n_writeh, a[0], tah, notif_wh);
$hold ( posedge pcg &&& n_writel, a[0], tah, notif_wl);
$hold ( posedge pcg &&& n_writeh, a[1], tah, notif_wh);
$hold ( posedge pcg &&& n_writel, a[1], tah, notif_wl);
$hold ( posedge pcg &&& n_writeh, a[2], tah, notif_wh);
$hold ( posedge pcg &&& n_writel, a[2], tah, notif_wl);
$hold ( posedge pcg &&& n_writeh, a[3], tah, notif_wh);
$hold ( posedge pcg &&& n_writel, a[3], tah, notif_wl);
$hold ( posedge pcg &&& n_writeh, a[4], tah, notif_wh);
$hold ( posedge pcg &&& n_writel, a[4], tah, notif_wl);
$hold ( posedge pcg &&& n_writeh, a[5], tah, notif_wh);
$hold ( posedge pcg &&& n_writel, a[5], tah, notif_wl);
$hold ( posedge pcg &&& n_writeh, a[6], tah, notif_wh);
$hold ( posedge pcg &&& n_writel, a[6], tah, notif_wl);
$hold ( posedge pcg &&& n_writeh, a[7], tah, notif_wh);
$hold ( posedge pcg &&& n_writel, a[7], tah, notif_wl);
$hold ( posedge pcg &&& n_readh, a[0], tah, notif_rh);
$hold ( posedge pcg &&& n_readl, a[0], tah, notif_rl);
$hold ( posedge pcg &&& n_readh, a[1], tah, notif_rh);
$hold ( posedge pcg &&& n_readl, a[1], tah, notif_rl);
$hold ( posedge pcg &&& n_readh, a[2], tah, notif_rh);
$hold ( posedge pcg &&& n_readl, a[2], tah, notif_rl);
$hold ( posedge pcg &&& n_readh, a[3], tah, notif_rh);
$hold ( posedge pcg &&& n_readl, a[3], tah, notif_rl);
$hold ( posedge pcg &&& n_readh, a[4], tah, notif_rh);
$hold ( posedge pcg &&& n_readl, a[4], tah, notif_rl);
$hold ( posedge pcg &&& n_readh, a[5], tah, notif_rh);
$hold ( posedge pcg &&& n_readl, a[5], tah, notif_rl);
$hold ( posedge pcg &&& n_readh, a[6], tah, notif_rh);
$hold ( posedge pcg &&& n_readl, a[6], tah, notif_rl);
$hold ( posedge pcg &&& n_readh, a[7], tah, notif_rh);
$hold ( posedge pcg &&& n_readl, a[7], tah, notif_rl);
$hold ( posedge pcg &&& n_writeh, web[1], twh, notif_wh);
$hold ( posedge pcg &&& n_writel, web[0], twh, notif_wl);
$hold ( posedge pcg &&& n_readh, web[1], twh, notif_rh);
$hold ( posedge pcg &&& n_readl, web[0], twh, notif_rl);
$hold ( posedge pcg &&& n_writeh, di[0], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[0], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[1], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[1], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[2], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[2], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[3], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[3], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[4], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[4], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[5], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[5], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[6], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[6], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[7], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[7], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[8], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[8], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[9], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[9], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[10], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[10], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[11], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[11], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[12], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[12], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[13], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[13], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[14], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[14], tdh, notif_wl);
$hold ( posedge pcg &&& n_writeh, di[15], tdh, notif_wh);
$hold ( posedge pcg &&& n_writel, di[15], tdh, notif_wl);
$hold ( posedge pcg , csb, tch, notif_c);
endspecify
`endif
//// input & output primitive gate.
buf (_csb, csb);
buf (_webh, web[1]);
buf (_webl, web[0]);
buf (_pcg, pcg);
/****************************************************************/
buf ( _diln[0] , di[0] );
buf ( _diln[1] , di[1] );
buf ( _diln[2] , di[2] );
buf ( _diln[3] , di[3] );
buf ( _diln[4] , di[4] );
buf ( _diln[5] , di[5] );
buf ( _diln[6] , di[6] );
buf ( _diln[7] , di[7] );
buf ( _dihn[8] , di[8] );
buf ( _dihn[9] , di[9] );
buf ( _dihn[10] , di[10] );
buf ( _dihn[11] , di[11] );
buf ( _dihn[12] , di[12] );
buf ( _dihn[13] , di[13] );
buf ( _dihn[14] , di[14] );
buf ( _dihn[15] , di[15] );
buf ( _an[0], a[0] );
buf ( _an[1], a[1] );
buf ( _an[2], a[2] );
buf ( _an[3], a[3] );
buf ( _an[4], a[4] );
buf ( _an[5], a[5] );
buf ( _an[6], a[6] );
buf ( _an[7], a[7] );
// bufif1 ( do0, qdol[0] ,oen );
buf ( dout[0], qdol[0] );
// bufif1 ( do1, qdol[1] ,oen );
buf ( dout[1], qdol[1] );
// bufif1 ( do2, qdol[2] ,oen );
buf ( dout[2], qdol[2] );
// bufif1 ( do3, qdol[3] ,oen );
buf ( dout[3], qdol[3] );
// bufif1 ( do4, qdol[4] ,oen );
buf ( dout[4], qdol[4] );
// bufif1 ( do5, qdol[5] ,oen );
buf ( dout[5], qdol[5] );
// bufif1 ( do6, qdol[6] ,oen );
buf ( dout[6], qdol[6] );
// bufif1 ( do7, qdol[7] ,oen );
buf ( dout[7], qdol[7] );
// bufif1 ( do8, qdoh[8] ,oen );
buf ( dout[8], qdoh[8] );
// bufif1 ( do9, qdoh[9] ,oen );
buf ( dout[9], qdoh[9] );
// bufif1 ( do10, qdoh[10] ,oen );
buf ( dout[10], qdoh[10] );
// bufif1 ( do11, qdoh[11] ,oen );
buf ( dout[11], qdoh[11] );
// bufif1 ( do12, qdoh[12] ,oen );
buf ( dout[12], qdoh[12] );
// bufif1 ( do13, qdoh[13] ,oen );
buf ( dout[13], qdoh[13] );
// bufif1 ( do14, qdoh[14] ,oen );
buf ( dout[14], qdoh[14] );
// bufif1 ( do15, qdoh[15] ,oen );
buf ( dout[15], qdoh[15] );
/****************************************************************/
buf ( _dil[0] , _diln[0] );
buf ( _dil[1] , _diln[1] );
buf ( _dil[2] , _diln[2] );
buf ( _dil[3] , _diln[3] );
buf ( _dil[4] , _diln[4] );
buf ( _dil[5] , _diln[5] );
buf ( _dil[6] , _diln[6] );
buf ( _dil[7] , _diln[7] );
buf ( _dih[8] , _dihn[8] );
buf ( _dih[9] , _dihn[9] );
buf ( _dih[10] , _dihn[10] );
buf ( _dih[11] , _dihn[11] );
buf ( _dih[12] , _dihn[12] );
buf ( _dih[13] , _dihn[13] );
buf ( _dih[14] , _dihn[14] );
buf ( _dih[15] , _dihn[15] );
buf ( _a[0], _an[0] );
buf ( _a[1], _an[1] );
buf ( _a[2], _an[2] );
buf ( _a[3], _an[3] );
buf ( _a[4], _an[4] );
buf ( _a[5], _an[5] );
buf ( _a[6], _an[6] );
buf ( _a[7], _an[7] );
/****************************************************************/
//// do timing generation for read
assign #td r_doh = qqdoh;
assign #td r_dol = qqdol;
assign #td w_doh = qqdoh;
assign #td w_dol = qqdol;
assign qdoh = ( r_doh & {8{we_regh}}) |
( w_doh & {8{~we_regh}});
assign qdol = ( r_dol & {8{we_regl}}) |
( w_dol & {8{~we_regl}});
///// ram cell.
reg[15:8] ram_primh[0:(2<<8)-1];
reg[7:0] ram_priml[0:(2<<8)-1];
//// mode definition.
assign n_writeh = (~_csb & ~_webh); // writeh
assign n_writel = (~_csb & ~_webl); // writel
assign n_readh = (~_csb & _webh); // readh
assign n_readl = (~_csb & _webl); // readl
// assign n_portd = _csb; // macro disable / port disable
////write_h
always @(posedge _pcg) begin
if(n_writeh==1'b1) begin
if(_a<=255) begin
ram_primh[_a] = _dih;
qqdoh = _dih;
we_regh = _webh ;
end
else begin
qqdoh = 8'bx;
we_regh = _webh ;
end
end
else
we_regh = _webh ;
end
////write_l
always @(posedge _pcg) begin
if(n_writel==1'b1) begin
if(_a<=255) begin
ram_priml[_a] = _dil;
qqdol = _dil;
we_regl = _webl ;
end
else begin
qqdol = 8'bx;
we_regl = _webl ;
end
end
else
we_regl = _webl ;
end
//// read_h
always @(posedge _pcg) begin
if(n_readh==1'b1) begin
if(_a<=255)begin
qqdoh = ram_primh[_a];
we_regh = _webh;
end
else begin
qqdoh = 8'bx;
we_regh = _webh;
end
end
else
we_regh = _webh;
end
//// read_l
always @(posedge _pcg) begin
if(n_readl==1'b1) begin
if(_a<=255)begin
qqdol = ram_priml[_a];
we_regl = _webl;
end
else begin
qqdol = 8'bx;
we_regl = _webl;
end
end
else
we_regl = _webl;
end
//// output port control
// assign oen = ~n_portd;
`ifdef functional
`else
//// timing violation ( insert x value when timing violation occur )
always @(notif_wh) begin
ram_primh[_a] = {8{1'bx}};
qqdoh = {8{1'bx}};
end
always @(notif_wl) begin
ram_priml[_a] = {8{1'bx}};
qqdol = {8{1'bx}};
end
always @(notif_rh or notif_c) begin
qqdoh = {8{1'bx}};
end
always @(notif_rl or notif_c) begin
qqdol = {8{1'bx}};
end
`endif
//// inhibition
always @(_csb) begin
if(_pcg == 1'b0) begin
$display("\n ** error !! ( time %0d ) **\n",$time);
$display(" can not change csb when pcg=0 \n");
end
end
//// error message
always @(_a) begin
if(n_writeh==1'b1 && _pcg == 1'b0) begin
$display("\n ** error !! ( time %0d ) **\n",$time);
$display(" can not change address during data write\n");
end
if(n_writel==1'b1 && _pcg == 1'b0) begin
$display("\n ** error !! ( time %0d ) **\n",$time);
$display(" can not change address during data write\n");
end
if(n_readh==1'b1 && _pcg == 1'b0) begin
$display("\n ** error !! ( time %0d ) **\n",$time);
$display(" can not change address during data read\n");
end
if(n_readl==1'b1 && _pcg == 1'b0) begin
$display("\n ** error !! ( time %0d ) **\n",$time);
$display(" can not change address during data read\n");
end
end
always @(_webh) begin
if(_pcg == 1'b0) begin
$display("\n ** error !! ( time %0d ) **\n",$time);
$display(" can not change web[1] when pcg=0 \n");
end
end
always @(_webl) begin
if(_pcg == 1'b0) begin
$display("\n ** error !! ( time %0d ) **\n",$time);
$display(" can not change web[0] when pcg=0 \n");
end
end
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine