module ao03d2 (zn, a1, a2, b1, b2, c);
   input a1, a2, b1, b2, c;
   output zn;
   and                  G2(N2, a1, a2),
                        G3(N3, b1, b2);
   not                  G4(zn, N5);
   or                   G5(N5, N2, N3, c);
endmodule