module me41d1 (z, i0, i1, i2, i3, s0, s1, en);
   input i0, i1, i2, i3, s0, s1, en;
   output z;
`ifdef SYNTH
    reg hold_z;
    buf b1(z, hold_z);
    always @(i0 or i1 or i2 or i3 or s0 or s1 or en)
       case ({en,s1,s0})
           3'b000: {hold_z} = i0;
           3'b001: {hold_z} = i1;
           3'b010: {hold_z} = i2;
           3'b011: {hold_z} = i3;
           3'b100: {hold_z} = 1'b0;
           3'b101: {hold_z} = 1'b0;
           3'b110: {hold_z} = 1'b0;
           3'b111: {hold_z} = 1'b0;
       endcase
`else
   and                  G2(N2, N13, N11, i0),
                        G3(z, N7, N12),
                        G4(N4, N13, s0, i1);
   or                   G7(N7, N2, N4, N8, N14);
   and                  G8(N8, s1, N11, i2);
   not                  G11(N11, s0),
                        G12(N12, en),
                        G13(N13, s1);
   and                  G14(N14, s1, s0, i3);
`endif
endmodule