module mx41d2 (z, i0, i1, i2, i3, s0, s1);
   input i0, i1, i2, i3, s0, s1;
   output z;
`ifdef SYNTH
    reg iz;
    buf (z,iz);
    always @(s0 or s1 or i0 or i1 or i2 or i3)
       case ({s1,s0})
           2'b00:  iz = i0;
           2'b01:  iz = i1;
           2'b10:  iz = i2;
           2'b11:  iz = i3;
       endcase
`else
   and                  G3(N3, N12, N10, i0);
   or                   G4(z, N3, N5, N9, N8);
   and                  G5(N5, N12, s0, i1),
                        G8(N8, s1, s0, i3),
                        G9(N9, s1, N10, i2);
   not                  G10(N10, s0),
                        G12(N12, s1);
`endif
endmodule