module mx42d1 (z, zn, i0, i1, i2, i3, s0, s1);
   input i0, i1, i2, i3, s0, s1;
   output z, zn;
`ifdef SYNTH
    reg iz;
    buf (z,  iz);
    not (zn, iz);
    always @(s0 or s1 or i0 or i1 or i2 or i3)
       case ({s1,s0})
           2'b00:  iz = i0;
           2'b01:  iz = i1;
           2'b10:  iz = i2;
           2'b11:  iz = i3;
       endcase
`else
   and                  G2(N2, N13, N11, i0);
   buf                  E0(z, J$z);
   and                  G4(N4, N13, s0, i1);
   or                   G7(J$z, N2, N4, N8, N14);
   and                  G8(N8, s1, N11, i2);
   not                  G11(N11, s0),
                        G12(zn, J$z),
                        G13(N13, s1);
   and                  G14(N14, s1, s0, i3);
`endif
endmodule