module mx81d1 (z, i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2);
   input i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2;
   output z;
`ifdef SYNTH
    reg iz;
    buf (z,iz);
    always @(i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7 or s0 or s1 or s2)
       case ({s2,s1,s0})
           3'b000: iz = i0;
           3'b001: iz = i1;
           3'b010: iz = i2;
           3'b011: iz = i3;
           3'b100: iz = i4;
           3'b101: iz = i5;
           3'b110: iz = i6;
           3'b111: iz = i7;
       endcase
`else
   and                  G3(N3, N19, N17, N15, i0);
   or                   G4(z, N3, N5, N10, N14, N18, N9, N16, N13);
   and                  G5(N5, N19, N17, s0, i1),
                        G9(N9, s2, N17, s0, i5),
                        G10(N10, N19, s1, N15, i2),
                        G13(N13, s2, s1, s0, i7),
                        G14(N14, N19, s1, s0, i3);
   not                  G15(N15, s0);
   and                  G16(N16, s2, s1, N15, i6);
   not                  G17(N17, s1);
   and                  G18(N18, s2, N17, N15, i4);
   not                  G19(N19, s2);
`endif
endmodule