module mx82d1 (z, zn, i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2);
   input i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2;
   output z, zn;
`ifdef SYNTH
    reg iz;
    buf (z,iz);
    not (zn, iz);
    always @(i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7 or s0 or s1 or s2)
       case ({s2,s1,s0})
           3'b000: iz = i0;
           3'b001: iz = i1;
           3'b010: iz = i2;
           3'b011: iz = i3;
           3'b100: iz = i4;
           3'b101: iz = i5;
           3'b110: iz = i6;
           3'b111: iz = i7;
       endcase
`else
   and                  G2(N2, N20, N18, N16, i0);
   or                   G3(J$z, N2, N4, N9, N13, N15, N21, N8, N14);
   and                  G4(N4, N20, N18, s0, i1),
                        G8(N8, s2, s1, N16, i6),
                        G9(N9, N20, s1, N16, i2);
   not                  G12(zn, J$z);
   and                  G13(N13, N20, s1, s0, i3),
                        G14(N14, s2, s1, s0, i7),
                        G15(N15, s2, N18, N16, i4);
   not                  G16(N16, s0),
                        G18(N18, s1);
   buf                  E0(z, J$z);
   not                  G20(N20, s2);
   and                  G21(N21, s2, N18, s0, i5);
`endif
endmodule