at.ss
2.79 KB
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/* Echo start time */
sh "date"
/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = "at"
default_max_transition = 2.5
hdlin_force_use_ffgen = false
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = search_path \
+ "../src" \
+ "../../inc" \
+ "../../syn"
read -f edif at_ew.edf
read -f edif at_tc.edf
read -f edif at_cc.edf
read -f edif at_bl.edf
read -f edif at_ms.edf
read -f verilog module + ".v"
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }
set_max_transition default_max_transition current_design
/*****************************************************************************/
/* clock and I/O timing, drive & load */
/*****************************************************************************/
include "at.tmg"
set_false_path -fall -from reset_l
dont_touch_network reset_l
set_dont_touch { ne35hd130d/lan* }
/*****************************************************************************/
/* check */
/*****************************************************************************/
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
characterize { atbl atcc atew atms attc }
current_design = at_bl
set_load 0.8 {blend_color}
compile -incremental_mapping
current_design = at_cc
compile -incremental_mapping
current_design = at_ew
set_load 0.8 {strobe_sync_full}
compile -incremental_mapping
current_design = at_ms
compile -incremental_mapping
current_design = at_tc
compile -incremental_mapping
current_design = at
/*****************************************************************************/
/* write */
/*****************************************************************************/
include "at.tmg"
include "report.dc"
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module
/* Echo end time */
sh "date"
quit