current_design = bl

/* operating conditions */
set_operating_conditions NOM
set_wire_load 256000 -mode top

/* clock */
create_clock gclk -period 16.0 -waveform {0 8.0}
set_driving_cell -none {gclk}
set_dont_touch_network {gclk}

/* default constraints */
set_input_delay 2.0 -clock gclk all_inputs() > /dev/null
set_output_delay 14.5 -clock gclk all_outputs() > /dev/null
set_driving_cell -cell dfntnb all_inputs() > /dev/null
set_load 0.08 all_outputs() > /dev/null

/* clock drive */
set_drive 0 {gclk}
set_arrival 0 {gclk}


/* custom constratints */
set_input_delay 4.0 -clock gclk { mem_a }
set_input_delay 4.0 -clock gclk { mem_b }
set_input_delay 4.0 -clock gclk { mem_g }
set_input_delay 4.0 -clock gclk { mem_r }
set_input_delay 3.0 -clock gclk { mem_z }
set_input_delay 5.0 -clock gclk { mask15b }
set_input_delay 5.0 -clock gclk { st_span }
set_input_delay 0.0 -clock gclk { dzdx dzdy }