cc.ss
3.35 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
/* Echo start time */
sh "date"
module = cc
search_path = search_path + "../src" + "../../inc" + \
"../../../lib/verilog/user" + "../../syn"
/* read the verilog sources */
read -f verilog ../src/cc_abs16n.v
read -f verilog ../src/cc_add12.v
read -f verilog ../src/cc_cvg_alpha.v
read -f verilog ../src/cc_edge_add.v
read -f verilog ../src/cc_edge_booth.v
read -f verilog ../src/cc_edge_booth0.v
read -f verilog ../src/cc_edge_booth1.v
read -f verilog ../src/cc_edge_booth2.v
read -f verilog ../src/cc_edge_csa.v
read -f verilog ../src/cc_edge_ctrl.v
read -f verilog ../src/cc_edge_div.v
read -f verilog ../src/cc_inc4.v
read -f verilog ../src/cc_key.v
read -f verilog ../src/cc_key_gt.v
read -f verilog ../src/cc_key_mux.v
read -f verilog ../src/cc_key_clamp.v
read -f verilog ../src/cc_lerp.v
read -f verilog ../src/cc_lerp_booth.v
read -f verilog ../src/cc_lerp_booth0.v
read -f verilog ../src/cc_lerp_booth7.v
read -f verilog ../src/cc_lerp_booth8.v
read -f verilog ../src/cc_lerp_csa.v
read -f verilog ../src/cc_lerp_csa_add12.v
read -f verilog ../src/cc_lerp_csa_fa10.v
read -f verilog ../src/cc_lerp_csa_fa11.v
read -f verilog ../src/cc_lerp_csa_fa14.v
read -f verilog ../src/cc_lerp_csa_fa8.v
read -f verilog ../src/cc_lerp_csa_fa9.v
read -f verilog ../src/cc_lerp_csa_faso.v
read -f verilog ../src/cc_lerp_csa_ha1.v
read -f verilog ../src/cc_lerp_csa_ha3.v
read -f verilog ../src/cc_lerp_csa_ha5.v
read -f verilog ../src/cc_mxaa.v
read -f verilog ../src/cc_mxar.v
read -f verilog ../src/cc_mxca.v
read -f verilog ../src/cc_mxcr.v
read -f verilog ../src/cc_mxxa.v
read -f verilog ../src/cc_mxxr.v
read -f verilog ../src/cc_mxya.v
read -f verilog ../src/cc_mxyr.v
read -f verilog ../src/cc.v
current_design = cc
link
check_design > cc.lint
/* compile restrictions */
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnr }
sub_modules = { cc_mxxr, cc_mxxa, cc_mxyr, cc_mxya, \
cc_mxar, cc_mxaa, cc_mxcr, cc_mxca, \
cc_lerp_booth, \
cc_abs16n, cc_add12, cc_cvg_alpha, cc_inc4, \
cc_edge_ctrl, cc_edge_add, \
cc_key_clamp, cc_key_gt, cc_key_mux, \
cc_edge_booth, cc_edge_csa, cc_edge_div, \
cc_key}
foreach(module, sub_modules){
set_dont_touch module
}
set_dont_touch cc_lerp_csa_add12
set_dont_touch cc_lerp_csa_fa10
set_dont_touch cc_lerp_csa_fa11
set_dont_touch cc_lerp_csa_fa14
set_dont_touch cc_lerp_csa_fa8
set_dont_touch cc_lerp_csa_fa9
set_dont_touch cc_lerp_csa_faso
set_dont_touch cc_lerp_csa_ha1
set_dont_touch cc_lerp_csa_ha3
set_dont_touch cc_lerp_csa_ha5
current_design = cc_lerp_csa
/* setup operating conditions */
set_operating_conditions NOM
set_wire_load 256000 -mode top
set_max_transition 1.1 current_design
set_load 0.08 all_outputs()
compile -map_effort low -incremental_mapping
current_design = cc_lerp
/* setup operating conditions */
set_operating_conditions NOM
set_wire_load 128000 -mode top
set_max_transition 1.1 current_design
set_load 0.08 all_outputs()
compile -map_effort low -incremental_mapping -ungroup_all
set_dont_touch current_design
current_design = cc
/* clock and I/O timing, drive & load */
include "cc.tmg"
/* area constraint */
max_area 10000
/* max transition design rule */
set_max_transition 1.1 current_design
/* compile */
compile -map_effort high -ungroup_all
/* standard reports & netlist */
module = cc
include "cc.tmg"
include "report.dc"
write -f edif -o cc.edf -hier cc
/* Echo end time */
sh "date"
quit