module = csgclk

/* set up a new search path */
search_path = search_path + "../../inc"

/* read the verilog source and netlists*/

read -f verilog ../src/csgclk.v
read -f edif csdecode.edf
read -f edif csfiforptr.edf
read -f edif csshuffle.edf

current_design = csgclk

/* compile restrictions
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* } */

/* setup operating conditions */

set_operating_conditions NOM
set_wire_load 256000 -mode top

/* compile */

set_dont_touch csdecode
set_dont_touch csfiforptr
set_dont_touch csshuffle

compile -map_effort low -incremental_mapping 

report_reference

report_constraint -all_violators

write -f edif -o csgclk.edf -hier csgclk

quit