module = cspartdec

/* set up a new search path */
search_path = search_path + "../../inc"


/* read the verilog sources */

read -f verilog ../src/cspartdec.v

current_design = cspartdec

/* compile restrictions
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* } */

/* setup operating conditions */

set_operating_conditions NOM
set_wire_load 256000 -mode top

link 

check_design > cspartdec.lint

/* timing/area constraints */

/* inputs */
set_driving_cell -cell dfntnh {fifo_out_cmd[*]}
set_driving_cell -cell nr05d2 {state_zero}
/* outputs */
set_max_delay 3.0 -to all_outputs()
set_max_delay 1.0 -to {one_word_cmd}
set_max_delay 1.0 -to {size_prim[*]}
set_max_transition 0.8 current_design
set_load 0.04 size_prim[*]
set_load 0.12 one_word_cmd

max_area 130 

/* compile */

set_flatten true -effort high
set_structure false

compile -map_effort high -ungroup_all

report -reference

report_constraint -all_violators

write -f edif -o cspartdec.edf -hier cspartdec

quit