module = csshuffle

/* set up a new search path */
search_path = search_path + "../../inc"


/* read the verilog sources */

read -f verilog ../src/csshuffle.v
read -f verilog ../src/csadder5b.v
read -f edif csshuftbl.edf

current_design = csshuffle

/* compile restrictions
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* } */

/* setup operating conditions */

set_operating_conditions NOM
set_wire_load 256000 -mode top

link 

check_design > csshuffle.lint

set_dont_touch csadder5b
set_dont_touch csshuftbl

/* timing/area constraints */

create_clock gclk -period 14.0 -waveform {7.0 14.0}
/* inputs */
set_input_delay 2.0 -clock gclk {cmd[*]}
set_input_delay 2.0 -clock gclk {base_adrs[*]}
set_input_delay 13.0 -clock gclk {inc_shf_state}
set_driving_cell -cell or03d2 {inc_shf_state}
set_driving_cell -cell dfntnb {cmd[*]}
set_driving_cell -cell dfctnh {base_adrs[*]}

/* outputs */
set_output_delay 6.0 -clock gclk {rm_addr[*], rl_addr[*]}
set_output_delay 13.0 -clock gclk {shf_state[*]}
set_output_delay 11.0 -clock gclk {update_shf}
set_load 0.08 all_outputs()

set_max_transition 0.8 current_design; 


/* compile */

compile -map_effort high -ungroup_all -boundary_optimization

report -reference

report_constraint -all_violators

write -f edif -o csshuffle.edf -hier csshuffle

quit