module = ep

search_path = search_path + "../src" + "../../inc" + \
   "../../../lib/verilog/user" + "../../syn"


/* read the verilog sources */

read -f verilog ../src/ep.v
read -f verilog ../src/ep_cc.v
read -f verilog ../src/ep_tc.v

current_design = ep

/* compile restrictions */
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnr }

/* setup operating conditions */

set_operating_conditions NOM
set_wire_load 256000 -mode top


/* timing/area constraints */

create_clock gclk -period 16.0 -waveform {0 8.0}

set_input_delay 3.0 -clock gclk all_inputs()

set_driving_cell -cell dfntnb -pin q all_inputs()

set_max_transition 1.5 current_design

set_driving_cell -none {gclk}
set_dont_touch_network {gclk}
set_drive 0 {gclk}
set_arrival 0 gclk

set_load 0.2 all_outputs()
set_max_delay 4.0 all_outputs()

/* compile */

link 

check_design > ep.lint

current_design = ep_tc
set_register_type -flip_flop dfntnh -exact find(cell, d_3d_reg*)

current_design = ep
compile_fix_multiple_port_nets = "true"
compile_no_new_cells_at_top_level = "true"
compile -map_effort medium

/* standard reports & netlist */

include "ep.tmg"
include "report.dc"

write -f edif -o ep.edf -hier ep

quit