/* setup aliases */

alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
				        set_wire_load 256000 -mode top;"
alias set_default_timing_constraints "create_clock gclk -period 16.0 -waveform {0.0 8.0}; \
				      set_input_delay 4.0 -clock gclk all_inputs(); \
				      set_output_delay 2.0 -clock gclk all_outputs(); \
				      set_max_delay 3.0 -to all_outputs(); \
				      set_load 0.2 all_outputs();"

/* read the verilog sources */

read -f verilog ../src/ewaddr.v

current_design = ewaddr

link 

check_design > ewaddr.lint

set_default_operating_conditions
create_clock gclk -period 16.0 -waveform {0.0 8.0}
set_max_transition 1.5 current_design
set_drive 0 {gclk, reset_l}
set_dont_touch_network {gclk}
set_clock_skew -uncertainty 1 gclk
fix_hold gclk

/* inputs */
set_input_delay 2.0 -clock gclk {width_cimage[*], width_timage[*]}
set_input_delay 3.0 -clock gclk {load_cmd_image}
set_input_delay 4.0 -clock gclk {x_sc_major[*], x_minor[*]}
set_input_delay 2.0 -clock gclk {yh[*]}
set_input_delay 4.0 -clock gclk {start_mult}
set_input_delay 4.0 -clock gclk {addr_newspan}
/* driving cells */
set_driving_cell -cell dfntnb {width_cimage[*], width_timage[*]}
set_driving_cell -cell dfntnb {load_cmd_image}
set_driving_cell -cell dfntnb {x_sc_major[*], x_minor[*]}
set_driving_cell -cell dfntnb {yh[*]}
set_driving_cell -cell nr05d1 {start_mult}
set_driving_cell -cell nr04d1 {addr_newspan}
/* outputs */
set_output_delay 13.0 -clock gclk {ew_ms_addr[*]}
set_load 0.08 all_outputs()
set_load 0.80 {ew_ms_addr[*]}
/* set_dont_use find(cell, "ne35hd130d/*1h") */

compile -map_effort high -ungroup_all

report -reference

report_constraint -all_violators

write -f edif -o ewaddr.edf -hier ewaddr

quit