/* setup aliases */

alias set_default_operating_conditions \
	"set_operating_conditions NOM -library rcp.db; \
	set_wire_load 256000 -mode top;"
alias set_default_timing_constraints \
	"create_clock clk -period 16.0 -waveform {0 8.0}; \
	set_input_delay 4.0 -clock clk all_inputs(); \
	set_output_delay -max 2.0 -clock clk all_outputs(); \
	fix_hold clk; \
	dont_touch_network clk; \
	set_drive 0 {clk}; \
	set_load 1 all_outputs();"


/* read the verilog sources */

search_path = {. \
	/ecad/synopsys/current/libraries/syn \
	/ecad/reality/lib/synopsys/nec35_v2.1 \
	/ecad/reality/lib/synopsys/rcp_lib};

read -f verilog ../src/lsctl.v
read -f edif ls_ex_rot_values.edf
read -f verilog ../../../lib/verilog/user/asdff.v
read -f verilog ../../../lib/verilog/user/asdffen.v

current_design = lsctl

dont_touch u_ex_rot_values

set_default_operating_conditions
set_default_timing_constraints
set_max_transition 2.00 current_design;


include	lsctl.con

link 

check_design > lsctl.lint

compile -map_effort high -ungroup_all

remove_attribute u_ex_rot_values dont_touch
ungroup -flatten u_ex_rot_values

compile -map_effort high -incremental_mapping

report -reference

report_constraint -all_violators

report_timing -path full -delay max -max_paths 20;

write -f edif -o lsctl.edf -hier lsctl
write -f verilog -o lsctl.vsyn -hier lsctl

quit