set_input_delay 8.0 -clock clk {reset_l};
set_input_delay 2.5 -clock clk {halt};
 
set_input_delay 3.0 -clock clk {pc};
 
set_input_delay 2.5 -clock clk {vu_ex_st_dec};
set_input_delay 2.0 -clock clk {ex_su_byte_ls};
set_input_delay 2.0 -clock clk {ex_su_half_ls};
set_input_delay 2.0 -clock clk {ex_mfc0};
set_input_delay 3.0 -clock clk {cp0_write};
set_input_delay 9.0 -clock clk {ex_dma_wen_swap};
set_input_delay 9.0 -clock clk {ex_dma_wen_noswap};
set_input_delay 13.0 -clock clk {mem_write_data};
set_input_delay 8.0 -clock clk {ex_rot};
set_input_delay 1.8 -clock clk {wb_rot};
 
set_input_delay 2.0 -clock clk {wb_pass_thru};
set_input_delay 2.0 -clock clk {wb_mfc2};
set_input_delay 2.0 -clock clk {wb_cfc2};
set_input_delay 2.7 -clock clk {wb_su_uns_ls};
set_input_delay 2.7 -clock clk {wb_su_load};
set_input_delay 1.5 -clock clk {dmem_dataout};
set_input_delay 2.0 -clock clk {vu_wb_ld_dec};
set_input_delay 4.0 -clock clk {ls_drive_ls};
set_input_delay 2.0 -clock clk {wb_dma_dm_to_rd};

set_input_delay 4.0 -clock clk {ls_data};
set_input_delay 9.0 -clock clk {cp0_data};

set_output_delay -max 4.0 -clock clk {ls_data_out};
set_output_delay -max 6.0 -clock clk {cp0_data_out};

set_output_delay -max 6.0 -clock clk {df_datain}; 
set_output_delay -max 7.5 -clock clk {dmem_rd_data};


set_driving_cell -cell dfntnb all_inputs()
set_driving_cell -cell ni01d5 -pin z {dmem_dataout};
set_driving_cell -none  clk
set_drive 0 clk


set_load 2.0 {ls_data_out};
set_load .7 {cp0_data_out};
set_load 1.5 {dmem_rd_data};

group_path -name non_dmem_rd_group -to all_outputs();
group_path -default -to {dmem_rd_data, ls_data};
group_path -name dmem_rd_group -to {dmem_rd_data};
group_path -name ls_data_group -to {ls_data};