/* setup aliases */

alias set_default_operating_conditions \
	"set_operating_conditions NOM -library rcp.db; \
	set_wire_load 256000 -mode top;"
alias set_default_timing_constraints \
	"create_clock clk -period 16.0 -waveform {0 8.0}; \
	set_input_delay 4.0 -clock clk all_inputs(); \
	set_output_delay 2.0 -clock clk all_outputs(); \
	fix_hold clk; \
	dont_touch_network clk; \
	set_drive 0 {clk}; \
	set_load 1 all_outputs();"

/* setup the search path for includes */
search_path = {. \
	/ecad/synopsys/current/libraries/syn \
	/ecad/reality/lib/synopsys/nec35_v2.1 \
	/ecad/reality/lib/synopsys/rcp_lib};

search_path = search_path + "../../inc" 

/* read the verilog sources */

read -f verilog ../src/lsdp.v
read -f verilog ../../../lib/verilog/user/asdff.v
read -f verilog ../../../lib/verilog/user/asdffen.v
read -f verilog ../../../lib/verilog/user/cp0_driver.v

current_design = lsdp

ungroup -flatten ls_dp_to_dmem_0th
ungroup -flatten ls_dp_to_dmem_1st
ungroup -flatten ls_dp_to_dmem_2nd
ungroup -flatten ls_dp_to_dmem_3rd

ungroup -flatten ls_dmem_to_dp_1st
ungroup -flatten ls_dmem_to_dp_2nd

ungroup -flatten cp0_driver_ls

dont_touch ls_dp_to_dmem_0th*
dont_touch ls_dp_to_dmem_1st*
dont_touch ls_dp_to_dmem_2nd*
dont_touch ls_dp_to_dmem_3rd*

dont_touch ls_dmem_to_dp_1st*
dont_touch ls_dmem_to_dp_2nd*

dont_touch ls_data_driver
dont_touch cp0_driver_ls*

dont_touch_network ls_data_out

current_design = lsdp

set_default_operating_conditions
set_default_timing_constraints
set_max_transition 2.00 current_design;


include	lsdp.con

link 

check_design > lsdp.lint

ungroup -flatten -all
compile -map_effort high
compile -map_effort high -incremental_mapping


report -reference

report_constraint -all_violators

report_timing -path full -from ex_rot[*] -delay max -max_paths 4;
report_timing -path full -delay max -max_paths 20;

write -f edif -o lsdp.edf -hier lsdp
write -f verilog -o lsdp.vsyn -hier lsdp

quit