ms.tmg
3.16 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = "ms"
wire_load = 256000
standard_load = 0.01
clock = "clock"
clocks = { clock gclock }
default_input_delay = 1.5
default_output_delay = 13.0
default_input_load = 20
default_output_load = 20
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 1.0
current_design = module
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* clock constraints */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
create_clock gclock -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clocks
set_dont_touch_network clocks
/*****************************************************************************/
/* default constraints */
/*****************************************************************************/
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 { clocks }
set_max_transition default_max_transition current_design
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_input_delay 10.0 -clock clock { cbus_data dbus_data ebus_data }
set_input_delay 5.0 -clock clock { cbus_read_enable cbus_write_enable }
set_input_delay 5.0 -clock clock { dma_read_enable dma_write_enable }
set_output_delay 6.0 -clock clock { cbus_data dbus_data ebus_data }
set_input_delay 5.0 -clock clock { bist_done }
set_output_delay 11.0 -clock clock { pipe_busy load_dv bist_done }
set_output_delay 13.0 -clock clock { bist_go bist_check }
set_output_delay 4.0 -clock clock { start_gclk }
set_output_delay 12.0 -clock clock { rdramreq }
set_output_delay 12.0 -clock clock { copy_load }
set_output_delay 12.0 -clock clock { rdpralpha }
set_output_delay 12.0 -clock clock { rdramrw }
set_input_delay 3.5 -clock clock { spanbufmt }
set_input_delay 4.0 -clock clock { noise }
set_input_delay 4.0 -clock clock { stb_sync_full }
set_input_delay 4.0 -clock clock { startspant0 }