/************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: ri.v,v 1.1.1.1 2002/05/17 06:14:58 blythe Exp $

module ri (clock, reset_l,
   cbus_read_enable, cbus_write_enable, cbus_command,
   read_grant, rbus_data_in, rbus_extend_in, ack, nack,
   tst_c_ctl_en, tst_c_ctl_ld, tst_c_ctl_i,
   ready, start, last, read_request, sp_dbus_read_enable,
   mi_dbus_read_enable, span_dbus_read_enable, sp_dbus_write_enable,
   mi_dbus_write_enable, pi_dbus_write_enable, si_dbus_write_enable,
   span_dbus_write_enable, rbus_data_out, rbus_extend_out, rbus_control_out,
   rbus_enable_out, c_ctl_en, c_ctl_ld, c_ctl_i, rac_sel_in, rac_sel_out,
   stop_t, stop_r,
   cbus_data, dbus_data, ebus_data);

`include "ri.vh"

parameter COUNT_SIZE					= 8;
parameter RAS_AGAIN_COUNT_SIZE	= 4;
parameter WORD_COUNT_SIZE			= COUNT_SIZE - DMA_OFFSET_SIZE;

parameter REFRESH_ADDRESS	= 32'h0008_001c;
parameter REFRESH_DATA		= 80'h0000_0000_0001_0000_0001;

parameter
	RBUS_ENABLE_RESET		= 8'b11111111,
	RBUS_ENABLE_ACTIVE	= 8'b11000000,
	RBUS_ENABLE_STANDBY	= 8'b00000000;

parameter
	CLEAN_MISS_DELAY		= 5,
	DIRTY_MISS_DELAY		= 7,
	READ_HIT_DELAY			= 5,
	WRITE_HIT_DELAY		= 1,
	RAS_AGAIN_DELAY		= -8,
	UNKNOWN_DELAY			= 'bx;

parameter
	RBUS_ENABLE_SHIFT_0	= 2'b00,
	RBUS_ENABLE_SHIFT_6	= 2'b01,
	RBUS_ENABLE_SHIFT_10	= 2'b1x;

parameter
	RBUS_DATA_SHIFT_0		= 0,
	RBUS_DATA_SHIFT_4		= 1;

parameter
	BLOCK_MASK_SIZE		= 2,
	BLOCK_MASK				= 8'b11111100;

parameter
	DMA_LATENCY_SIZE		= 4,
	SERIAL_COUNT_SIZE		= 4;

	
input clock;
input reset_l;

input cbus_read_enable;
input cbus_write_enable;
input [CBUS_COMMAND_SIZE-1:0] cbus_command;
input read_grant;
input [RBUS_DATA_SIZE-1:0] rbus_data_in;
input [RBUS_EXTEND_SIZE-1:0] rbus_extend_in;
input ack;
input nack;
input tst_c_ctl_en;
input tst_c_ctl_ld;
input [RAC_CURRENT_SIZE-1:0] tst_c_ctl_i;

output ready;
output start;
output last;
output read_request;
output sp_dbus_read_enable;
output mi_dbus_read_enable;
output span_dbus_read_enable;
output sp_dbus_write_enable;
output mi_dbus_write_enable;
output pi_dbus_write_enable;
output si_dbus_write_enable;
output span_dbus_write_enable;
output [RBUS_DATA_SIZE-1:0] rbus_data_out;
output [RBUS_EXTEND_SIZE-1:0] rbus_extend_out;
output [RBUS_CONTROL_SIZE-1:0] rbus_control_out;
output [RBUS_ENABLE_SIZE-1:0] rbus_enable_out;
output c_ctl_en;
output c_ctl_ld;
output [RAC_CURRENT_SIZE-1:0] c_ctl_i;
output [RAC_SELECT_SIZE-1:0] rac_sel_in;
output [RAC_SELECT_SIZE-1:0] rac_sel_out;
output stop_t;
output stop_r;

inout [CBUS_DATA_SIZE-1:0] cbus_data;
inout [DBUS_DATA_SIZE-1:0] dbus_data;
inout [EBUS_DATA_SIZE-1:0] ebus_data;

// output pseudo registers
reg sp_dbus_write_enable;
reg mi_dbus_write_enable;
reg pi_dbus_write_enable;
reg si_dbus_write_enable;
reg span_dbus_write_enable;
reg ri_dbus_write_enable;
reg sp_dbus_read_enable;
reg mi_dbus_read_enable;
reg span_dbus_read_enable;
reg ri_dbus_read_enable;

// resetable registers
reg ready;
reg start;
reg last;
reg read_request;
reg ri_c_ctl_en;
reg ri_c_ctl_ld;
reg [RAC_CURRENT_SIZE-1:0] ri_c_ctl_i;
reg [RAC_SELECT_SIZE-1:0] rac_sel_out;
reg [RAC_SELECT_SIZE-1:0] rac_sel_in;
reg stop_t0;
reg stop_t1;
reg stop_t2;
reg stop_t3;
reg stop_r0;
reg stop_r1;
reg stop_r2;
reg [DMA_DEVICE_SIZE-1:0] dbus_write_enable;
reg [DMA_DEVICE_SIZE-1:0] dbus_read_enable;
reg [OPERATING_MODE_SIZE-1:0] operating_mode;
reg [COUNT_SIZE-1:0] start_count;
reg [COUNT_SIZE-1:0] end_count;
reg [COUNT_SIZE-1:0] ready_count;
reg [WORD_COUNT_SIZE-1:0] last_count;
reg [COUNT_SIZE-1:0] memory_count;
reg [COUNT_SIZE-1:0] rw_hazard_count;
reg [1:0] device_count;
reg [RAS_AGAIN_COUNT_SIZE-1:0] ras_again_count;
reg dirty0, dirty1, dirty2, dirty3, dirty4, dirty5, dirty6, dirty7;
reg valid0, valid1, valid2, valid3, valid4, valid5, valid6, valid7;
reg rbus_select0;
reg rbus_select1;
reg rbus_select2;
reg rbus_select3;
reg rbus_select4;
reg start_request;
reg memory_request;
reg last_active;
reg dbus_read_disable;
reg refresh_bank;
reg refresh_enable;
reg refresh_optimize;
reg [NUM_MULTIBANKS-1:0] refresh_multibank;
reg rbus_request_ack;
reg rbus_request_nack;
reg ack_error;
reg nack_error;
reg over_range;
reg stop_r_active;
reg stop_t_active;
reg [DMA_LATENCY_SIZE-1:0] dma_latency;
reg [RI_REG_ADDRESS_SIZE-1:0] reg_address;
reg [COUNT_SIZE-1:0] start_offset;
reg row_dirty;
reg row_active;
reg request_read;
reg [DMA_LENGTH_SIZE-1:0] request_length;
reg request_dma_masked;
reg request_dma_down;
reg request_dma_nseq;
reg request_dma_subblock;
reg [DMA_DEVICE_SIZE-1:0] request_read_device;
reg [DMA_DEVICE_SIZE-1:0] request_write_device;
reg request_config;
reg request_refresh;
reg [BLOCK_MASK_SIZE-1:0] request_block_mask;
reg [SERIAL_ADDRESS_SIZE-1:0] serial_address;
reg dma_masked_pl;
reg dma_down_pl;
reg dma_nseq_pl;
reg dma_subblock_pl;
reg rbus_data_shift;
reg [RBUS_ENABLE_SHIFT_SIZE-1:0] rbus_enable_shift;

// non resetable registers
reg [RBUS_CONTROL_SIZE-1:0] rbus_control_reg;
reg [RBUS_ENABLE_SIZE-1:0] rbus_enable_reg;
reg [DMA_DEVICE_SIZE-1:0] read_device_pl;
reg [DMA_DEVICE_SIZE-1:0] write_device_pl;
reg [COUNT_SIZE-1:0] clean_refresh_delay;
reg [COUNT_SIZE-1:0] dirty_refresh_delay;
reg [RBUS_DATA_SIZE-1:0] rbus_data_reg;
reg [RBUS_EXTEND_SIZE-1:0] rbus_extend_reg;
reg [ROW_SIZE-1:0] row0, row1, row2, row3, row4, row5, row6, row7;
reg [REQUEST_ADDRESS_SIZE-1:0] address_pl;
reg [DMA_LENGTH_SIZE-1:0] length_pl;
reg read_pl;
reg config_pl;
reg refresh_pl;
reg [REQUEST_ADDRESS_SIZE-1:0] request_address;
reg ack_reg;
reg nack_reg;
reg rbus_request_ack_d1;
reg rbus_request_ack_d2;
reg rbus_request_ack_d3;
reg rbus_request_ack_d4;
reg rbus_request_ack_d5;
reg rbus_request_nack_d1;
reg rbus_request_nack_d2;
reg rbus_request_nack_d3;
reg rbus_request_nack_d4;
reg [CBUS_COMMAND_SIZE-1:0] cbus_command_reg;
reg [CBUS_DATA_SIZE-1:0] cbus_data_reg;
reg [DBUS_DATA_SIZE-1:0] dbus_data_reg;
reg [EBUS_DATA_SIZE-1:0] ebus_data_reg;
reg [RBUS_EXTEND_SIZE/2-1:0] rbus_extend_d0_high;
reg [RBUS_DATA_SIZE/2-1:0] rbus_data_d0_high;
reg [RBUS_CONTROL_SIZE/2-1:0] rbus_control_d0_high;
reg [1:0] rbus_enable_d0_low, rbus_enable_d0_high, rbus_enable_d1_high;
reg [3:0] rbus_enable_d0_mid;

// non-resetable latches
reg [RBUS_DATA_SIZE-1:0] rbus_data_out;
reg [RBUS_EXTEND_SIZE-1:0] rbus_extend_out;
reg [RBUS_CONTROL_SIZE-1:0] rbus_control_out;
reg [RBUS_ENABLE_SIZE-1:0] rbus_enable_out;


// dma state machine
reg [2:0] cbus_state;
parameter
	STATE_CBUS_IDLE			= 0,
	STATE_CBUS_WRITE_LENGTH	= 1,
	STATE_CBUS_REFRESH		= 2,
	STATE_CBUS_WRITE_RI		= 3,
	STATE_CBUS_READ_RI		= 4;


// ready state machine
reg [1:0] start_state;
parameter
	STATE_START_IDLE			= 0,
	STATE_START_BUSY			= 1,
	STATE_START_LAST			= 2;


// memory state machine
reg [3:0] memory_state;
parameter
	STATE_MEMORY_IDLE			= 0,
	STATE_MEMORY_WAIT			= 1,
	STATE_MEMORY_REQUEST		= 2,
	STATE_MEMORY_MISS_1		= 3,
	STATE_MEMORY_MISS_2		= 4,
	STATE_MEMORY_MISS_3		= 5,
	STATE_MEMORY_MISS_4		= 6,
	STATE_MEMORY_MISS_5		= 7,
	STATE_MEMORY_MISS_6		= 8,
	STATE_MEMORY_MISS_7		= 9,
	STATE_MEMORY_REFRESH_1	= 10,
	STATE_MEMORY_REFRESH_2	= 11,
	STATE_MEMORY_REFRESH_3	= 12;



always @(dbus_write_enable) begin
	ri_dbus_write_enable = LOW;
	sp_dbus_write_enable = LOW;
	mi_dbus_write_enable = LOW;
	pi_dbus_write_enable = LOW;
	si_dbus_write_enable = LOW;
	span_dbus_write_enable = LOW;

	case (dbus_write_enable)
		BUS_DEVICE_RI : ri_dbus_write_enable = HIGH;
		BUS_DEVICE_SP : sp_dbus_write_enable = HIGH;
		BUS_DEVICE_MI : mi_dbus_write_enable = HIGH;
		BUS_DEVICE_PI : pi_dbus_write_enable = HIGH;
		BUS_DEVICE_SI : si_dbus_write_enable = HIGH;
		BUS_DEVICE_DP_SPAN : span_dbus_write_enable = HIGH;
		default : ri_dbus_write_enable = HIGH;
		endcase
	end


always @(dbus_read_enable or dbus_read_disable) begin
	ri_dbus_read_enable = LOW;
	sp_dbus_read_enable = LOW;
	mi_dbus_read_enable = LOW;
	span_dbus_read_enable = LOW;

	if (!dbus_read_disable)	case (dbus_read_enable)
		BUS_DEVICE_RI : ri_dbus_read_enable = HIGH;
		BUS_DEVICE_SP : sp_dbus_read_enable = HIGH;
		BUS_DEVICE_MI : mi_dbus_read_enable = HIGH;
		BUS_DEVICE_DP_CMD : sp_dbus_read_enable = HIGH;
		BUS_DEVICE_DP_SPAN : span_dbus_read_enable = HIGH;
		endcase
	end


// bus drivers
wire ri_ebus_write_enable;
assign ri_ebus_write_enable = ri_dbus_write_enable | sp_dbus_write_enable
  | pi_dbus_write_enable | si_dbus_write_enable;
cbus_driver cbus_driver_0(cbus_data_reg,    cbus_write_enable, cbus_data);
dbus_driver dbus_driver_0(dbus_data_reg, ri_dbus_write_enable, dbus_data);
ebus_driver ebus_driver_0(ebus_data_reg, ri_ebus_write_enable, ebus_data);

assign stop_r = stop_r2;
assign stop_t = stop_t3;
assign c_ctl_en = ri_c_ctl_en | tst_c_ctl_en;
assign c_ctl_ld = ri_c_ctl_ld | tst_c_ctl_ld;
assign c_ctl_i = ri_c_ctl_i | tst_c_ctl_i;

// split up rbus_request to ease drive
wire [RBUS_DATA_SIZE/4-1:0] rbus_data0;
wire [RBUS_DATA_SIZE/4-1:0] rbus_data1;
wire [RBUS_DATA_SIZE/4-1:0] rbus_data2;
wire [RBUS_DATA_SIZE/4-1:0] rbus_data3;
wire [DBUS_DATA_SIZE/4-1:0] dbus_data0;
wire [DBUS_DATA_SIZE/4-1:0] dbus_data1;
wire [DBUS_DATA_SIZE/4-1:0] dbus_data2;
wire [DBUS_DATA_SIZE/4-1:0] dbus_data3;
wire [RBUS_DATA_SIZE/4-1:0] rbus_out0;
wire [RBUS_DATA_SIZE/4-1:0] rbus_out1;
wire [RBUS_DATA_SIZE/4-1:0] rbus_out2;
wire [RBUS_DATA_SIZE/4-1:0] rbus_out3;

assign {rbus_data0, rbus_data1, rbus_data2, rbus_data3} = rbus_data_reg;
assign {dbus_data0, dbus_data1, dbus_data2, dbus_data3} = dbus_data_reg;
assign rbus_out0 = rbus_select0 ? rbus_data0 : dbus_data0;
assign rbus_out1 = rbus_select1 ? rbus_data1 : dbus_data1;
assign rbus_out2 = rbus_select2 ? rbus_data2 : dbus_data2;
assign rbus_out3 = rbus_select3 ? rbus_data3 : dbus_data3;


wire [RBUS_EXTEND_SIZE/2-1:0] rbus_extend_low, rbus_extend_high;
wire [RBUS_DATA_SIZE/2-1:0] rbus_data_low, rbus_data_high;
wire [RBUS_CONTROL_SIZE/2-1:0] rbus_control_low, rbus_control_high;
wire [1:0] rbus_enable_low, rbus_enable_high;
wire [3:0] rbus_enable_mid;
wire [RBUS_EXTEND_SIZE-1:0] next_rbus_extend_out;
wire [RBUS_DATA_SIZE-1:0] next_rbus_data_out;
wire [RBUS_CONTROL_SIZE-1:0] next_rbus_control_out;
wire [RBUS_ENABLE_SIZE-1:0] next_rbus_enable_out;

assign {rbus_extend_low, rbus_extend_high}
  = rbus_select4 ? rbus_extend_reg : ebus_data_reg;
assign rbus_data_low = {rbus_out0, rbus_out1};
assign rbus_data_high = {rbus_out2, rbus_out3};
assign {rbus_control_low, rbus_control_high} = rbus_control_reg;
assign {rbus_enable_low, rbus_enable_mid, rbus_enable_high} = rbus_enable_reg;

assign next_rbus_extend_out = rbus_data_shift
  ? {rbus_extend_d0_high, rbus_extend_low}
  : {rbus_extend_low, rbus_extend_high};

assign next_rbus_data_out = rbus_data_shift
  ? {rbus_data_d0_high, rbus_data_low}
  : {rbus_data_low, rbus_data_high};

assign next_rbus_control_out = rbus_data_shift
  ? {rbus_control_d0_high, rbus_control_low}
  : {rbus_control_low, rbus_control_high};

assign next_rbus_enable_out = rbus_enable_shift[1]
	? {rbus_enable_d1_high, rbus_enable_d0_low, rbus_enable_d0_mid}
	: rbus_enable_shift[0]
		? {rbus_enable_d0_mid, rbus_enable_d0_high, rbus_enable_low}
		: {rbus_enable_low, rbus_enable_mid, rbus_enable_high};

always @(clock or next_rbus_extend_out or next_rbus_data_out
  or next_rbus_control_out or next_rbus_enable_out) begin
	if (!clock) begin
		rbus_extend_out = next_rbus_extend_out;
		rbus_data_out = next_rbus_data_out;
		rbus_control_out = next_rbus_control_out;
		rbus_enable_out = next_rbus_enable_out;
		end
	end

always @(posedge clock) begin : rbus_data_block
	rbus_extend_d0_high <= rbus_extend_high;
	rbus_data_d0_high <= rbus_data_high;
	rbus_control_d0_high <= rbus_control_high;
	{rbus_enable_d0_low, rbus_enable_d0_mid, rbus_enable_d0_high}
	  <= rbus_enable_reg;
	rbus_enable_d1_high <= rbus_enable_d0_high;
	end

always @(posedge clock) begin : cbus_data_block
	reg [CBUS_DATA_SIZE-1:0] cbus_data_out;

	case (reg_address[RI_REG_ADDRESS_SIZE-1:0])
		RI_MODE_REG : cbus_data_out = {stop_r_active, stop_t_active,
		  operating_mode};
		RI_CONFIG_REG : cbus_data_out = {ri_c_ctl_en, ri_c_ctl_i};
		RI_SELECT_REG : cbus_data_out = {rac_sel_out, rac_sel_in};
		RI_REFRESH_REG : cbus_data_out = {refresh_multibank, refresh_optimize,
		  refresh_enable, refresh_bank, dirty_refresh_delay, clean_refresh_delay};
		RI_LATENCY_REG : cbus_data_out = dma_latency;
		RI_ERROR_REG : cbus_data_out = {over_range, nack_error, ack_error};
		RI_VALID_REG : cbus_data_out = {dirty7, dirty6, dirty5, dirty4,
		  dirty3, dirty2, dirty1, dirty0, valid7, valid6, valid5,
		  valid4, valid3, valid2, valid1, valid0};
		default : cbus_data_out = 'bx;
		endcase

	ack_reg <= ack;
	nack_reg <= nack;
	rbus_request_ack_d1 <= rbus_request_ack;
	rbus_request_ack_d2 <= rbus_request_ack_d1;
	rbus_request_ack_d3 <= rbus_request_ack_d2;
	rbus_request_ack_d4 <= rbus_request_ack_d3;
	rbus_request_ack_d5 <= rbus_request_ack_d4;
	rbus_request_nack_d1 <= rbus_request_nack;
	rbus_request_nack_d2 <= rbus_request_nack_d1;
	rbus_request_nack_d3 <= rbus_request_nack_d2;
	rbus_request_nack_d4 <= rbus_request_nack_d3;
	cbus_command_reg <= cbus_command;
	cbus_data_reg <= cbus_read_enable ? cbus_data : cbus_data_out;
	dbus_data_reg <= ri_dbus_read_enable ? dbus_data : rbus_data_in;
	ebus_data_reg <= ri_dbus_read_enable
	  ? (sp_dbus_write_enable || pi_dbus_write_enable
	    || si_dbus_write_enable)
	    ? {{2{dbus_data[48]}}, {2{dbus_data[32]}},
	       {2{dbus_data[16]}}, {2{dbus_data[0]}}}
	    : ebus_data
	  : rbus_extend_in;
	end


always @(posedge clock or negedge reset_l) begin
	if (!reset_l) begin
		// resetable registers
		ready <= HIGH;
		start <= LOW;
		last <= LOW;
		read_request <= LOW;
		ri_c_ctl_en <= LOW;
		ri_c_ctl_ld <= LOW;
		ri_c_ctl_i <= 0;
		rac_sel_in <= 0;
		rac_sel_out <= 0;
		stop_t0 <= LOW;
		stop_t1 <= LOW;
		stop_t2 <= LOW;
		stop_t3 <= LOW;
		stop_r0 <= LOW;
		stop_r1 <= LOW;
		stop_r2 <= LOW;
		dbus_write_enable <= 0;
		dbus_read_enable <= 0;
		operating_mode <= RI_STANDBY_MODE;
		start_count <= 0;
		end_count <= 0;
		ready_count <= 0;
		last_count <= 0;
		memory_count <= 0;
		rw_hazard_count <= 0;
		device_count <= 1;
		ras_again_count <= 0;
		dirty0 <= HIGH;
		dirty1 <= HIGH;
		dirty2 <= HIGH;
		dirty3 <= HIGH;
		dirty4 <= HIGH;
		dirty5 <= HIGH;
		dirty6 <= HIGH;
		dirty7 <= HIGH;
		valid0 <= LOW;
		valid1 <= LOW;
		valid2 <= LOW;
		valid3 <= LOW;
		valid4 <= LOW;
		valid5 <= LOW;
		valid6 <= LOW;
		valid7 <= LOW;
		rbus_select0 <= HIGH;
		rbus_select1 <= HIGH;
		rbus_select2 <= HIGH;
		rbus_select3 <= HIGH;
		rbus_select4 <= HIGH;
		start_request <= LOW;
		memory_request <= LOW;
		last_active <= LOW;
		dbus_read_disable <= HIGH;
		refresh_bank <= LOW;
		refresh_enable <= LOW;
		refresh_optimize <= LOW;
		refresh_multibank <= 'b0;
		rbus_request_ack <= LOW;
		rbus_request_nack <= LOW;
		ack_error <= LOW;
		nack_error <= LOW;
      over_range <= LOW;
		stop_r_active <= HIGH;
		stop_t_active <= HIGH;
		dma_latency <= -1;
		reg_address <= 0;
		start_offset <= 0;
		row_dirty <= LOW;
		row_active <= LOW;
		request_read <= 0;
		request_length <= 0;
		request_dma_masked <= 0;
		request_dma_down <= 0;
		request_dma_nseq <= 0;
		request_dma_subblock <= 0;
		request_read_device <= 0;
		request_write_device <= 0;
		request_config <= 0;
		request_refresh <= 0;
		request_block_mask <= 0;
		serial_address <= 0;
		dma_masked_pl <= 0;
		dma_down_pl <= 0;
		dma_nseq_pl <= 0;
		dma_subblock_pl <= 0;
		rbus_data_shift <= 0;
		rbus_enable_shift <= 0;

		cbus_state <= STATE_CBUS_IDLE;
		memory_state <= STATE_MEMORY_IDLE;
		start_state <= STATE_START_IDLE;

		// non-resetable registers
		rbus_control_reg <= 'bx;
		rbus_enable_reg <= 'bx;
		read_device_pl <= 'bx;
		write_device_pl <= 'bx;
		dirty_refresh_delay <= 'bx;
		clean_refresh_delay <= 'bx;
		rbus_data_reg <= 'bx;
		rbus_extend_reg <= 'bx;
		row0 <= 'bx;
		row1 <= 'bx;
		row2 <= 'bx;
		row3 <= 'bx;
		row4 <= 'bx;
		row5 <= 'bx;
		row6 <= 'bx;
		row7 <= 'bx;
		address_pl <= 'bx;
		length_pl <= 'bx;
		read_pl <= 'bx;
		config_pl <= 'bx;
		refresh_pl <= 'bx;
		request_address <= 'bx;

		end
	else begin : main_block
		reg next_ri_c_ctl_ld;
		reg ri_reg_selected;
		reg next_rbus_select;
		reg next_read_request;
		reg load_ready_count;
		reg load_start_count;
		reg load_last_count;
		reg load_end_count;
		reg load_device_count;
		reg load_rw_hazard_count;
		reg load_ras_again_count;
		reg load_rbus_request_ack;
		reg load_rbus_request_nack;
		reg load_rbus_request_nexe;
		reg load_rbus_refresh;
		reg increment_serial_address;
		reg decrement_serial_address;
		reg generate_serial_address;
		reg next_start;
		reg next_last;
		reg next_ready;
		reg [COUNT_SIZE-1:0] next_start_offset;
		reg [COUNT_SIZE-1:0] next_start_count;
		reg [SERIAL_ADDRESS_SIZE-1:0] next_serial_address;
		reg [COUNT_SIZE-1:0] next_end_offset;
		reg [COUNT_SIZE-1:0] next_end_count;
		reg [SERIAL_ADDRESS_SIZE-1:0] serial_addend;
		reg next_dbus_read_disable;
		reg impending_request;
		reg stall;
		reg [SERIAL_ADDRESS_SIZE-1:0] masked_serial_address;
		reg [RBUS_ENABLE_SIZE-1:0] next_rbus_enable;
		reg next_stop_t0;
		reg next_stop_t2;
		reg next_stop_r;
		reg [REQUEST_OP_SIZE-1:0] op;
		reg [REQUEST_ADDRESS_SIZE-1:0] adr;
		reg [REQUEST_COUNT_SIZE-1:0] count;

		next_ri_c_ctl_ld = LOW;
		ri_reg_selected = (cbus_data_reg & BUS_ADDRESS_MASK) == BUS_ADDRESS_RI;
		next_rbus_select = HIGH;
		next_read_request = LOW;
		load_ready_count = LOW;
		load_start_count = LOW;
		load_last_count = LOW;
		load_end_count = LOW;
		load_device_count = LOW;
		load_rw_hazard_count = LOW;
		load_ras_again_count = LOW;
		load_rbus_request_ack = LOW;
		load_rbus_request_nack = LOW;
		load_rbus_request_nexe = LOW;
		load_rbus_refresh = LOW;
		increment_serial_address = LOW;
		decrement_serial_address = LOW;
		generate_serial_address = LOW;
		next_start = LOW;
		next_last = LOW;
		next_ready = HIGH;
		next_start_offset = start_offset;
		next_serial_address = serial_address;
		next_dbus_read_disable = LOW;
		next_end_offset = read_pl ? -3 : 0;
		next_end_count = memory_count + next_end_offset;
		next_start_count = end_count + start_offset;
		impending_request = LOW;
		stall = LOW;

		masked_serial_address = {
		   serial_address[0] ^ request_block_mask[0],
		   serial_address[1] ^ request_block_mask[1],
		   serial_address[2],
		   serial_address[3],
		   serial_address[4],
		   serial_address[5],
		   serial_address[6],
		   serial_address[7]
		   };

		next_stop_r = stop_r_active;
		next_stop_t0 = stop_t_active;
		next_stop_t2 = stop_t_active;

		case (operating_mode)
			RI_RESET_MODE : begin
				next_rbus_enable = RBUS_ENABLE_RESET;
				end

			RI_ACTIVE_MODE : begin
				next_rbus_enable = RBUS_ENABLE_ACTIVE;
				end

			RI_STANDBY_MODE : begin
				next_rbus_enable = RBUS_ENABLE_STANDBY;
				end

			default : begin
				// default to standby
				next_rbus_enable = RBUS_ENABLE_STANDBY;
				end
			endcase

		// deassert ready as soon as possible
		if (cbus_command == CBUS_DMA_COMMAND
		  || cbus_command == CBUS_REFRESH_COMMAND) next_ready = LOW;



		/************************* CBUS State Machine **************************/
		case (cbus_state)
			STATE_CBUS_IDLE : begin
				case (cbus_command_reg)
					CBUS_DMA_COMMAND : begin : cbus_dma_command
						reg [  CBUS_DATA_SIZE - (BANK_SIZE + ROW_SIZE
                       + COLUMN_SIZE + OFFSET_SIZE) - 1:0] next_over_range;
						reg [BANK_SIZE-1:0] next_bank;
						reg [ROW_SIZE-1:0] next_row;
						reg [COLUMN_SIZE-1:0] next_column;
						reg [OFFSET_SIZE-1:0] next_offset;
						reg next_rdram_valid;
						reg [ROW_SIZE-1:0] next_rdram_row;

						// write the DMA address/length register
						{next_over_range, next_bank, next_row, next_column,
							next_offset} = cbus_data_reg;

						next_ready = LOW;
						address_pl <= cbus_data_reg;
						refresh_pl <= LOW;
						cbus_state <= STATE_CBUS_WRITE_LENGTH;

						if ((cbus_data_reg & BUS_ADDRESS_MASK)
						  == BUS_ADDRESS_RDRAM_CONFIG) begin
                     // RDRAM register access
							config_pl <= HIGH;
							row_active <= HIGH;
							row_dirty <= LOW;
							end
						else if (next_over_range) begin
                     // outside range of bank/row tracking
	                  row_active <= HIGH;
                     row_dirty <= LOW;
	                  over_range <= HIGH;
                     $display("Panic!  RDRAM access out of range");
			            $finish;
                     end
                  else begin
							// RDRAM memory access
							config_pl <= LOW;
							case (next_bank) // synopsys full_case
								0 : begin
									next_rdram_valid = valid0;
									next_rdram_row = row0;

									valid0 <= HIGH;
									row0 <= next_row;
									row_dirty <= dirty0;
									end

								1 : begin
									next_rdram_valid = valid1;
									next_rdram_row = row1;

									valid1 <= HIGH;
									row1 <= next_row;
									row_dirty <= dirty1;
									end

								2 : begin
									next_rdram_valid = valid2;
									next_rdram_row = row2;

									valid2 <= HIGH;
									row2 <= next_row;
									row_dirty <= dirty2;
									end

								3 : begin
									next_rdram_valid = valid3;
									next_rdram_row = row3;

									valid3 <= HIGH;
									row3 <= next_row;
									row_dirty <= dirty3;
									end

								4 : begin
									next_rdram_valid = valid4;
									next_rdram_row = row4;

									valid4 <= HIGH;
									row4 <= next_row;
									row_dirty <= dirty4;
									end

								5 : begin
									next_rdram_valid = valid5;
									next_rdram_row = row5;

									valid5 <= HIGH;
									row5 <= next_row;
									row_dirty <= dirty5;
									end

								6 : begin
									next_rdram_valid = valid6;
									next_rdram_row = row6;

									valid6 <= HIGH;
									row6 <= next_row;
									row_dirty <= dirty6;
									end

								7 : begin
									next_rdram_valid = valid7;
									next_rdram_row = row7;

									valid7 <= HIGH;
									row7 <= next_row;
									row_dirty <= dirty7;
									end
								endcase

		  					row_active <= next_rdram_valid
 							   && (next_row == next_rdram_row);
							end
						end

					CBUS_REFRESH_COMMAND : begin
						if (refresh_enable) begin
							next_ready = LOW;
							address_pl <= REFRESH_ADDRESS;
							refresh_pl <= HIGH;
							config_pl <= HIGH;
							row_active <= LOW;
							refresh_bank <= ~refresh_bank;
							cbus_state <= STATE_CBUS_REFRESH;

							if (refresh_optimize) begin
								if (refresh_bank) begin
									row_dirty <=
									    dirty1 || dirty3 || dirty5 || dirty7
									 || (dirty0 && !refresh_multibank[0])
									 || (dirty2 && !refresh_multibank[1])
									 || (dirty4 && !refresh_multibank[2])
									 || (dirty6 && !refresh_multibank[3]);
									dirty0 <= dirty0 && refresh_multibank[0];
									dirty1 <= LOW;
									dirty2 <= dirty2 && refresh_multibank[1];
									dirty3 <= LOW;
									dirty4 <= dirty4 && refresh_multibank[2];
									dirty5 <= LOW;
									dirty6 <= dirty6 && refresh_multibank[3];
									dirty7 <= LOW;
									end
								else begin
									row_dirty <=
									    dirty0 || dirty2 || dirty4 || dirty6
									 || (dirty1 && !refresh_multibank[0])
									 || (dirty3 && !refresh_multibank[1])
									 || (dirty5 && !refresh_multibank[2])
									 || (dirty7 && !refresh_multibank[3]);
									dirty0 <= LOW;
									dirty1 <= dirty1 && refresh_multibank[0];
									dirty2 <= LOW;
									dirty3 <= dirty3 && refresh_multibank[1];
									dirty4 <= LOW;
									dirty5 <= dirty5 && refresh_multibank[2];
									dirty6 <= LOW;
									dirty7 <= dirty7 && refresh_multibank[3];
									end
								end
							else begin
								row_dirty <= HIGH;
								end
							end
						else begin
							cbus_state <= STATE_CBUS_IDLE;
							end
						end

					CBUS_WRITE_COMMAND : begin
						// write an RI config register
						if (ri_reg_selected) begin
							reg_address <= cbus_data_reg >> IO_OFFSET_SIZE;
							cbus_state <= STATE_CBUS_WRITE_RI;
							end
						else begin
							cbus_state <= STATE_CBUS_IDLE;
							end
						end

					CBUS_READ_COMMAND : begin
						// read an RI config register
						if (ri_reg_selected) begin
							next_read_request = HIGH;
							reg_address <= cbus_data_reg >> IO_OFFSET_SIZE;
							cbus_state <= STATE_CBUS_READ_RI;
							end
						else begin
							cbus_state <= STATE_CBUS_IDLE;
							end
						end

					default : begin
						cbus_state <= STATE_CBUS_IDLE;
						end
					endcase
				end

			STATE_CBUS_WRITE_LENGTH : begin : state_cbus_write_length
				reg [DMA_DEVICE_SIZE-1:0] device;
				reg [DMA_DELAY_SIZE-1:0] start_delay;
				reg next_read;
				reg [DMA_LENGTH_SIZE-1:0] byte_length;
				reg [DMA_LENGTH_SIZE-DMA_OFFSET_SIZE-1:0] word_length;
				reg [  CBUS_DATA_SIZE - (BANK_SIZE + ROW_SIZE
                 + COLUMN_SIZE + OFFSET_SIZE) - 1:0] over_range;
				reg [BANK_SIZE-1:0] bank;
				reg [ROW_SIZE-1:0] row;
				reg [COLUMN_SIZE-1:0] column;
				reg [OFFSET_SIZE-1:0] offset;
				reg [COUNT_SIZE-DMA_OFFSET_SIZE-1:0] last_offset;
				reg next_dma_subblock;
				reg next_dma_masked;
				reg next_dma_down;
				reg next_dma_nseq;
				reg [COUNT_SIZE-1:0] next_request_count;
				reg next_dirty;

				{next_dma_subblock, next_dma_masked, next_dma_down, next_dma_nseq,
				  device, start_delay, next_read, byte_length} = cbus_data_reg;

				word_length = byte_length >> DMA_OFFSET_SIZE;
				{over_range, bank, row, column, offset} = address_pl;
				impending_request = HIGH;
				next_ready = LOW;
				load_ready_count = HIGH;
				next_dirty = (row_active && row_dirty) || !next_read;

				if (!config_pl && !over_range) begin
					case (bank)
						0 : dirty0 <= next_dirty;
						1 : dirty1 <= next_dirty;
						2 : dirty2 <= next_dirty;
						3 : dirty3 <= next_dirty;
						4 : dirty4 <= next_dirty;
						5 : dirty5 <= next_dirty;
						6 : dirty6 <= next_dirty;
						7 : dirty7 <= next_dirty;
						endcase
					end

				case ({row_active, row_dirty, next_read})
					3'b000 : next_request_count = CLEAN_MISS_DELAY + WRITE_HIT_DELAY;
					3'b001 : next_request_count = CLEAN_MISS_DELAY + READ_HIT_DELAY;
					3'b010 : next_request_count = DIRTY_MISS_DELAY + WRITE_HIT_DELAY;
					3'b011 : next_request_count = DIRTY_MISS_DELAY + READ_HIT_DELAY;
					3'b100 : next_request_count = WRITE_HIT_DELAY;
					3'b101 : next_request_count = READ_HIT_DELAY;
					3'b110 : next_request_count = WRITE_HIT_DELAY;
					3'b111 : next_request_count = READ_HIT_DELAY;
					endcase

				if (next_read) begin
					read_device_pl <= device;
					write_device_pl <= BUS_DEVICE_RI;
					end
				else begin
					read_device_pl <= BUS_DEVICE_RI;
					write_device_pl <= device;
					end

				next_start_offset = next_request_count + start_delay;

				memory_count <= next_request_count + word_length + next_dma_masked;
				read_pl <= next_read;
				length_pl <= byte_length;
				dma_subblock_pl <= next_dma_subblock;
				dma_masked_pl <= next_dma_masked;
				dma_down_pl <= next_dma_down;
				dma_nseq_pl <= next_dma_nseq;

				if (start_request || memory_request) begin
					$display("%m: Panic!	RI not ready for a memory operation");
					$finish;
					end
				else begin
					start_request <= HIGH;
					memory_request <= HIGH;
					end

				cbus_state <= STATE_CBUS_IDLE;
				end

			STATE_CBUS_REFRESH : begin
				impending_request = HIGH;
				next_ready = LOW;

				if (row_dirty) begin
					memory_count <= dirty_refresh_delay;
					end
				else begin
					memory_count <= clean_refresh_delay;
					end

				read_pl <= LOW;

				if (start_request || memory_request) begin
					$display("%m: Panic!	RI not ready for a refresh");
					$finish;
					end
				else begin
					memory_request <= HIGH;
					end
				cbus_state <= STATE_CBUS_IDLE;
				end


			STATE_CBUS_WRITE_RI : begin
				case (reg_address[RI_REG_ADDRESS_SIZE-1:0])
					RI_MODE_REG : {stop_r_active, stop_t_active, operating_mode}
					  <= cbus_data_reg;
					RI_CONFIG_REG : {ri_c_ctl_en, ri_c_ctl_i} <= cbus_data_reg;
					RI_CURRENT_LOAD_REG : next_ri_c_ctl_ld = HIGH;
					RI_SELECT_REG : {rac_sel_out, rac_sel_in} <= cbus_data_reg;
					RI_REFRESH_REG : {refresh_multibank, refresh_optimize,
					  refresh_enable, refresh_bank, dirty_refresh_delay,
					  clean_refresh_delay} <= cbus_data_reg;
					RI_LATENCY_REG : dma_latency <= cbus_data_reg;
					RI_ERROR_REG : begin
						over_range <= LOW;
						nack_error <= LOW;
						ack_error <= LOW;
						end
					RI_VALID_REG : begin
						dirty0 <= HIGH;
						dirty1 <= HIGH;
						dirty2 <= HIGH;
						dirty3 <= HIGH;
						dirty4 <= HIGH;
						dirty5 <= HIGH;
						dirty6 <= HIGH;
						dirty7 <= HIGH;
						valid0 <= LOW;
						valid1 <= LOW;
						valid2 <= LOW;
						valid3 <= LOW;
						valid4 <= LOW;
						valid5 <= LOW;
						valid6 <= LOW;
						valid7 <= LOW;
						end
				endcase
				cbus_state <= STATE_CBUS_IDLE;
				end

			STATE_CBUS_READ_RI : begin
				if (read_grant) begin
					cbus_state <= STATE_CBUS_IDLE;
					end
				else begin
					next_read_request = HIGH;
					cbus_state <= STATE_CBUS_READ_RI;
					end
				end

			default : begin
				cbus_state <= 'bx;
				end
			endcase


		/************************* Stall Test ***********************/
		if (start_request) begin
			if (
			  // start-before-end hazard
			  (last_active &&
			  {3'b100, last_count} >=
			  {~next_start_count[COUNT_SIZE-1], next_start_count[COUNT_SIZE-2:0]})
			  // write-after-read dbus enable hazard
			  || (request_read && !read_pl && row_active &&
			  rw_hazard_count[COUNT_SIZE-1:0] &&
			  {~rw_hazard_count[COUNT_SIZE-1], rw_hazard_count[COUNT_SIZE-2:0]}
			  < {~ready_count[COUNT_SIZE-1], ready_count[COUNT_SIZE-2:0]})
			  // ras-again hazard
			  || (!row_active && ras_again_count[RAS_AGAIN_COUNT_SIZE-1] &&
			  {4'b0111, ras_again_count} <
			  {~ready_count[COUNT_SIZE-1], ready_count[COUNT_SIZE-2:0]})

			  ) begin
				load_ready_count = HIGH;
				stall = HIGH;
				end
			end


		/*********************** Start State Machine **************************/
		case (start_state)
			STATE_START_IDLE : begin
				if (start_request && !stall) begin
					start_request <= LOW;
					if ((next_start_count[COUNT_SIZE-1] || !next_start_count)) begin
						// next_start_count <= 0
						next_start = HIGH;
						start_state <= STATE_START_IDLE;
						end
					else begin
						if (next_start_count != 1) begin
							next_ready = LOW;
							end
						load_start_count = HIGH;
						start_state <= STATE_START_BUSY;
						end
					end
				else begin
					start_state <= STATE_START_IDLE;
					end
				end

			STATE_START_BUSY : begin
				if (start_count[COUNT_SIZE-1] || !start_count) begin
					// start_count <= 0
					next_start = HIGH;
					start_state <= STATE_START_IDLE;
					end
				else begin
					// start_count > 0
					if (start_count != 1) begin
						next_ready = LOW;
						end
					start_state <= STATE_START_BUSY;
					end
				end
			endcase



		/************************* Memory State Machine ***********************/
		case (memory_state)
			STATE_MEMORY_IDLE : begin
				rbus_data_shift <= RBUS_DATA_SHIFT_4;
				if (end_count) begin
					// transaction in progress
					if (!request_refresh) begin
						// memory (or register) read/write transaction
						if (request_dma_nseq) begin
							generate_serial_address = HIGH;
							next_rbus_enable = masked_serial_address;
							end

						if (request_read) begin
							next_stop_r = LOW;
							rbus_enable_shift <= RBUS_ENABLE_SHIFT_6;
							if (request_dma_nseq) begin
								// transmit serial address during read transaction
								next_stop_t2 = LOW;
								end
							end
						else begin
							next_stop_t2 = LOW;
							next_rbus_select = LOW;
							rbus_enable_shift <= RBUS_ENABLE_SHIFT_10;
							end
						end
					else begin
						rbus_enable_shift <= RBUS_ENABLE_SHIFT_10;
						end
					memory_state <= STATE_MEMORY_IDLE;
					end
				else if (memory_request && !ready_count[COUNT_SIZE-1]) begin
					// ready_count >= 0
					// transaction ready
					rbus_enable_shift <= RBUS_ENABLE_SHIFT_0;

					if (dma_nseq_pl) begin
						if (dma_subblock_pl) begin
							request_block_mask <= address_pl>>DMA_OFFSET_SIZE;
							next_serial_address
							  = ((address_pl>>DMA_OFFSET_SIZE) & BLOCK_MASK);
							end
						else begin
							request_block_mask <= 0;
							next_serial_address = (address_pl>>DMA_OFFSET_SIZE);
							end

						if (!dma_masked_pl) begin
							if (dma_down_pl) begin
								decrement_serial_address = HIGH;
								end
							else begin
								increment_serial_address = HIGH;
								end
							end
						end

					if (stall) begin
						// wait for hazard to clear
						memory_state <= STATE_MEMORY_IDLE;
						end
					else begin
						if (row_active && !read_pl) begin
							// enable dbus immediately for the upcoming write hit
							next_dbus_read_disable = HIGH;
							dbus_read_enable <= read_device_pl;
							dbus_write_enable <= write_device_pl;
							end

						memory_request <= LOW;
						request_address <= address_pl;
						request_read <= read_pl;
						request_length <= length_pl;
						request_dma_masked <= dma_masked_pl;
						request_dma_down <= dma_down_pl;
						request_dma_nseq <= dma_nseq_pl;
						request_read_device <= read_device_pl;
						request_write_device <= write_device_pl;
						request_config <= config_pl;
						request_refresh <= refresh_pl;
						next_rbus_enable = RBUS_ENABLE_ACTIVE;
						memory_state <= STATE_MEMORY_REQUEST;
						end
					end
				else begin
					// wait for a transaction
					rbus_enable_shift <= RBUS_ENABLE_SHIFT_0;
					memory_state <= STATE_MEMORY_IDLE;
					end
				end

			STATE_MEMORY_REQUEST : begin
				next_stop_t0 = LOW;
				load_end_count = HIGH;

				if (next_end_count >= dma_latency) begin
					// equivlant to end_count+1 > dma_latency
					next_ready = LOW;
					end

				if (request_refresh) begin
					// generate a refresh command
					load_rbus_request_nexe = HIGH;
					rbus_enable_shift <= RBUS_ENABLE_SHIFT_10;
					rbus_data_shift <= RBUS_DATA_SHIFT_4;
					memory_state <= STATE_MEMORY_REFRESH_1;
					end
				else if (request_config) begin
					// generate a register command
					load_rbus_request_nexe = HIGH;
					rbus_data_shift <= RBUS_DATA_SHIFT_4;
					if (request_read) begin
						load_device_count = HIGH;
						rbus_enable_shift <= RBUS_ENABLE_SHIFT_6;
						end
					else begin
						rbus_enable_shift <= RBUS_ENABLE_SHIFT_10;
						end
					memory_state <= STATE_MEMORY_IDLE;
					end
				else begin
					// generate a memory command
					if (row_active) begin
						load_rbus_request_ack = HIGH;
						generate_serial_address = HIGH;
						rbus_data_shift <= RBUS_DATA_SHIFT_4;
						if (request_read) begin
							load_device_count = HIGH;
							rbus_enable_shift <= RBUS_ENABLE_SHIFT_6;
							end
						else begin
							rbus_enable_shift <= RBUS_ENABLE_SHIFT_10;
							end
						memory_state <= STATE_MEMORY_IDLE;
						end
					else begin
						load_device_count = HIGH;
						load_rbus_request_nack = HIGH;
						rbus_enable_shift <= RBUS_ENABLE_SHIFT_0;
						rbus_data_shift <= RBUS_DATA_SHIFT_0;
						if (row_dirty) begin
							memory_state <= STATE_MEMORY_MISS_1;
							end
						else begin
							load_ras_again_count = HIGH;
							memory_state <= STATE_MEMORY_MISS_3;
							end
						end
					end
				end

			STATE_MEMORY_MISS_1 : begin
				rbus_enable_shift <= RBUS_ENABLE_SHIFT_0;
				rbus_data_shift <= RBUS_DATA_SHIFT_0;
				memory_state <= STATE_MEMORY_MISS_2;
				end

			STATE_MEMORY_MISS_2 : begin
				load_ras_again_count = HIGH;
				rbus_enable_shift <= RBUS_ENABLE_SHIFT_0;
				rbus_data_shift <= RBUS_DATA_SHIFT_0;
				memory_state <= STATE_MEMORY_MISS_3;
				end

			STATE_MEMORY_MISS_3 : begin
				rbus_enable_shift <= RBUS_ENABLE_SHIFT_0;
				rbus_data_shift <= RBUS_DATA_SHIFT_0;
				memory_state <= STATE_MEMORY_MISS_4;
				end

			STATE_MEMORY_MISS_4 : begin
				rbus_enable_shift <= RBUS_ENABLE_SHIFT_0;
				rbus_data_shift <= RBUS_DATA_SHIFT_0;
				memory_state <= STATE_MEMORY_MISS_5;
				end

			STATE_MEMORY_MISS_5 : begin
				next_stop_t0 = LOW;
				rbus_enable_shift <= RBUS_ENABLE_SHIFT_0;
				rbus_data_shift <= RBUS_DATA_SHIFT_0;
				memory_state <= STATE_MEMORY_MISS_6;
				end

			STATE_MEMORY_MISS_6 : begin
				next_stop_t0 = LOW;
				next_rbus_enable = RBUS_ENABLE_ACTIVE;
				rbus_enable_shift <= RBUS_ENABLE_SHIFT_0;
				rbus_data_shift <= RBUS_DATA_SHIFT_0;
				memory_state <= STATE_MEMORY_MISS_7;
				end

			STATE_MEMORY_MISS_7 : begin
				// generate a memory command
				next_stop_t0 = LOW;
				generate_serial_address = HIGH;
				load_rbus_request_ack = HIGH;

				rbus_data_shift <= RBUS_DATA_SHIFT_4;
				if (request_read) begin
					rbus_enable_shift <= RBUS_ENABLE_SHIFT_6;
					end
				else begin
					rbus_enable_shift <= RBUS_ENABLE_SHIFT_10;
					end

				memory_state <= STATE_MEMORY_IDLE;
				end

			STATE_MEMORY_REFRESH_1 : begin
				next_stop_t0 = LOW;
				load_rbus_refresh = HIGH;
				rbus_enable_shift <= RBUS_ENABLE_SHIFT_10;
				rbus_data_shift <= RBUS_DATA_SHIFT_4;
				memory_state <= STATE_MEMORY_REFRESH_2;
				end

			STATE_MEMORY_REFRESH_2 : begin
				rbus_enable_shift <= RBUS_ENABLE_SHIFT_10;
				rbus_data_shift <= RBUS_DATA_SHIFT_4;
				memory_state <= STATE_MEMORY_REFRESH_3;
				end

			STATE_MEMORY_REFRESH_3 : begin
				next_ri_c_ctl_ld = HIGH;
				rbus_enable_shift <= RBUS_ENABLE_SHIFT_10;
				rbus_data_shift <= RBUS_DATA_SHIFT_4;
				memory_state <= STATE_MEMORY_IDLE;
				end

			default : begin
				memory_state <= 'bx;
				end
			endcase


		if (load_end_count) begin
			rw_hazard_count <= ~memory_count;
			end_count <= next_end_count;
			end
		else begin
			if (end_count) begin
				end_count <= end_count - 1;
				end
			if (rw_hazard_count[COUNT_SIZE-1]) begin
				rw_hazard_count <= rw_hazard_count + 1;
				end
			end


		// load bus enable after read delay
		// Use a the fact that it stalls at 1 and reloads 2
		if (load_device_count || device_count != 1) begin
			device_count <= device_count + 1;
			end

		if (device_count == 0) begin
			next_dbus_read_disable = HIGH;
			dbus_read_enable <= request_read_device;
			dbus_write_enable <= request_write_device;
			end


		if (load_ready_count) begin
			ready_count <= next_start_offset;
			end
		else if (ready_count[COUNT_SIZE-1]) begin
			// ready_count < 0
			ready_count <= ready_count + 1;
			end


		if (load_start_count) begin
			start_count <= next_start_count - 1;
			end
		else if (!start_count[COUNT_SIZE-1] && start_count) begin
			// start_count > 0
			start_count <= start_count - 1;
			end


		// begin last count
		if (next_start) begin
			if (length_pl>>DMA_OFFSET_SIZE) begin
				last_count <= (length_pl>>DMA_OFFSET_SIZE) - 1;
				last_active <= HIGH;
				end
			else begin
				next_last = HIGH;
				end
			end


		// detect RDRAM ras-again hazard
		if (load_ras_again_count) begin
			ras_again_count <= RAS_AGAIN_DELAY;
			end
		else if (ras_again_count[RAS_AGAIN_COUNT_SIZE-1]) begin
			ras_again_count <= ras_again_count + 1;
			end


		if (last_active) begin
			if (last_count) begin
				last_count <= last_count - 1;
				end
			else begin
				next_last = HIGH;
				last_active <= LOW;
				end
			end


		if (generate_serial_address && request_dma_nseq) begin
			next_rbus_enable = masked_serial_address;
			if (request_dma_down) begin
				decrement_serial_address = HIGH;
				end
			else begin
				increment_serial_address = HIGH;
				end
			end


		if (decrement_serial_address) begin
			serial_addend = -1;
			end
		else if (increment_serial_address) begin
			serial_addend = 1;
			end
		else begin
			serial_addend = 0;
			end

		serial_address <= next_serial_address + serial_addend;
		if ((impending_request || memory_request) && end_count < 2) begin
			next_stop_t0 = LOW;
			end

		// generate the next request packet

		if (request_config) begin : config_block
			reg global;
			reg [RDRAM_DEVICE_ID_SIZE-1:0] device_id;
			reg [RDRAM_REG_ADDRESS_SIZE-1:0] reg_address;

			{global, device_id, reg_address} = request_address;
			adr = {device_id, 10'b0, reg_address};
			count = 3;

			if (request_read) begin
				op = OP_READ_REG;
				end
			else if (global) begin
				op = OP_WRITE_REG_GLOBAL;
				end
			else begin
				op = OP_WRITE_REG;
				end
			end
		else begin
			adr = request_address;
			count = request_length;

			if (request_dma_masked) begin
				op = OP_WRITE_MEM_MASK;
				end
			else if (request_dma_nseq) begin
				if (request_read) begin
					op = OP_READ_MEM_NSEQ;
					end
				else begin
					op = OP_WRITE_MEM_NSEQ;
					end
				end
			else if (request_read) begin
				op = OP_READ_MEM_SEQ;
				end
			else begin
				op = OP_WRITE_MEM_SEQ;
				end
			end

		case (HIGH) // synopsys parallel_case
			load_rbus_request_ack,
			load_rbus_request_nack,
			load_rbus_request_nexe :
			{rbus_control_reg, rbus_extend_reg, rbus_data_reg} <= {
			  1'b1, op[1], op[5], op[2], op[4], 3'b0,
			  op[0], op[3], adr[26], adr[35], 4'b0,
			  adr[9:2],
			  adr[17:10],
			  adr[25:18],
			  adr[34:27],
			  1'b0, count[6], count[4], count[2], 4'b0,
			  1'b0, count[7], count[5], count[3], count[1:0], adr[1:0],
			  8'b0,
			  8'b0
			  };

			load_rbus_refresh :
			{rbus_control_reg, rbus_extend_reg, rbus_data_reg}
			  <= REFRESH_DATA;

			default : 
			{rbus_control_reg, rbus_extend_reg, rbus_data_reg}
			  <= 0;
			endcase

		if (rbus_request_ack_d5 && !ack_reg) begin
			ack_error <= HIGH;
			$display("Panic!  ACK expected");
			$finish;
			end

		if (rbus_request_nack_d4 && !nack_reg) begin
			nack_error <= HIGH;
			$display("Panic!  NACK expected");
			$finish;
			end

		rbus_enable_reg <= next_rbus_enable;
		ri_c_ctl_ld <= next_ri_c_ctl_ld;
		rbus_select0 <= next_rbus_select;
		rbus_select1 <= next_rbus_select;
		rbus_select2 <= next_rbus_select;
		rbus_select3 <= next_rbus_select;
		rbus_select4 <= next_rbus_select;
		read_request <= next_read_request;
		start <= next_start;
		last <= next_last;
		ready <= next_ready && !memory_request
		  && (end_count <= dma_latency);
		stop_t0 <= next_stop_t0;
		stop_t1 <= stop_t0 && next_stop_t0;
		stop_t2 <= stop_t1 && next_stop_t2 && next_stop_t0;
		stop_t3 <= stop_t2 && next_stop_t2 && next_stop_t0;
		stop_r0 <= next_stop_r;
		stop_r1 <= stop_r0 & next_stop_r;
		stop_r2 <= stop_r1 & next_stop_r;
		start_offset <= next_start_offset;
		dbus_read_disable <= next_dbus_read_disable;
		rbus_request_ack <= load_rbus_request_ack;
		rbus_request_nack <= load_rbus_request_nack;
		end
	end
endmodule