ri.ss
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = "ri"
wire_load = 128000
standard_load = 0.01
clock = "clock"
default_input_delay = 1.5
default_output_delay = 13.0
default_pin_delay = 10.0
default_input_load = 20
default_output_load = 20
default_pin_load = 150
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 2.0
default_uncertainty = 1.0
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = {. \
/ecad/synopsys/current/libraries/syn \
/ecad/reality/lib/synopsys/nec35_v2.1 \
/ecad/reality/lib/synopsys/rcp_lib};
search_path = search_path \
+ "../src" \
+ "../../inc" \
+ "../../../lib/verilog/user" \
+ "../../syn"
read -f verilog cbus_driver.v
read -f verilog dbus_driver.v
read -f verilog ebus_driver.v
read -f verilog module + ".v"
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* clock constraints */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clock
set_dont_touch_network clock
set_fix_hold all_clocks()
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 { clock }
set_input_delay 0 { clock }
set_max_transition default_max_transition current_design
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_driving_cell -cell ni01d5 { cbus_read_enable cbus_write_enable }
set_driving_cell -cell nt01d5 { cbus_data dbus_data ebus_data }
set_load 350 * standard_load { cbus_data dbus_data ebus_data }
set_input_delay 10.0 -clock clock { cbus_data dbus_data ebus_data }
set_output_delay 6.0 -clock clock { cbus_data dbus_data ebus_data }
set_driving_cell -cell ni01d5 { cbus_command }
set_load 300 * standard_load { cbus_command }
set_max_fanout 2 * standard_load { cbus_command }
set_load 170 * standard_load { *_dbus_read_enable *_dbus_write_enable }
set_load 2.0 { span_dbus_read_enable }
set_load 2.0 { span_dbus_write_enable }
set_output_delay 10.0 -clock clock { sp_dbus_read_enable }
set_output_delay 10.0 -clock clock { mi_dbus_read_enable }
set_output_delay 10.0 -clock clock { span_dbus_read_enable }
set_output_delay 10.0 -clock clock { sp_dbus_write_enable }
set_output_delay 10.0 -clock clock { mi_dbus_write_enable }
set_output_delay 10.0 -clock clock { pi_dbus_write_enable }
set_output_delay 10.0 -clock clock { si_dbus_write_enable }
set_output_delay 10.0 -clock clock { span_dbus_write_enable }
set_max_transition 1.5 { *_dbus_read_enable *_dbus_write_enable }
set_load 400 * standard_load { start last }
set_load 1.3 { ready }
set_load 1.0 { read_request }
set_max_transition 1.0 { start last ready }
set_max_fanout 2 * standard_load { rbus_data_in rbus_extend_in ack nack }
set_output_delay -max 10.0 -clock clock { c_ctl_i c_ctl_en c_ctl_ld }
set_load 150 * standard_load { c_ctl_i c_ctl_en c_ctl_ld }
set_max_transition 1.0 { c_ctl_i c_ctl_en c_ctl_ld }
set_output_delay 5.0 -clock clock \
{ rbus_data_out rbus_extend_out rbus_control_out rbus_enable_out }
set_max_fanout 2 * standard_load reset_l
/*****************************************************************************/
/* check */
/*****************************************************************************/
link
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
set_register_type -latch lanfnh -exact find(cell, rbus_extend_out_reg[*])
set_register_type -latch lanfnh -exact find(cell, rbus_data_out_reg[*])
set_register_type -latch lanfnh -exact find(cell, rbus_control_out_reg[*])
set_register_type -latch lanfnh -exact find(cell, rbus_enable_out_reg[*])
compile -map_effort high -ungroup_all
/*****************************************************************************/
/* write */
/*****************************************************************************/
include "report.dc"
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module
quit