st.ss
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module = st
search_path = search_path + "../src" + "../../inc" + \
"../../../lib/verilog/user" + "../../syn"
/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 256000 -mode top;"
alias set_default_timing_constraints "create_clock gclk -period 16.0 -waveform {8.0 16.0}; \
set_input_delay 2.0 -clock gclk all_inputs(); \
set_output_delay 2.0 -clock gclk all_outputs(); \
set_max_transition 1.0 current_design; \
set_load 0.08 all_outputs();"
/* read the verilog sources */
read -f edif strgba.edf
read -f edif ststwl.edf
read -f edif stz.edf
read -f verilog ../src/st.v
set_dont_touch strgba
set_dont_touch ststwl
set_dont_touch stz
current_design = st
set_default_operating_conditions
set_default_timing_constraints
link
check_design > st.lint
current_design = st
compile -map_effort low -ungroup_all -incremental_mapping
report -reference
report_constraint -all_violators
include "st.tmg"
include "report.dc"
write -f edif -o st.edf -hier st
quit