/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
// $Id: issue.v,v 1.1.1.1 2002/05/17 06:14:58 blythe Exp $

// issue.v: 	RSP issue logic

`timescale 1ns / 10ps

module issue (clk, reset_l, halt, single_step, 
	pc_in_wr_en, pc_data_in, halting, 
	br_addr, rd_inst, set_broke, 
	imem_dma_pif, 
	taken, adv_ir, kill_re, 
	su_inst, vu_inst, su_nop_debug, vu_nop_debug, 
	link_pc_delay_pc, pc, 
	kill_su_issue, kill_vu_issue, store_xpose_rd);

   input		clk;
   input		reset_l;
   input		halt;
   input		single_step;
   input		pc_in_wr_en;
   input	[11:2]	pc_data_in;
   input		halting;
   input	[11:2]	br_addr;
   input  	[63:0]  rd_inst;	// imem out.  [63:32] is low order inst
   input		set_broke;
   input		imem_dma_pif;
   input 		taken;
   input		adv_ir;
   input		kill_re;

   output	[31:0]	su_inst;
   output	[31:0]	vu_inst;
   output		su_nop_debug;		// RD stage to nowhere
   output		vu_nop_debug;		// RD stage to nowhere
   output	[23:0]	link_pc_delay_pc;	// EX stage to LS
   output  	[11:2]  pc;
   output 		kill_su_issue;
   output		kill_vu_issue;
   output		store_xpose_rd;		// Moved from suvuctl for timing

   // Generation of these outputs is moved from suvuctl for timing reasons.

   wire			should_have_stalled;   
   wire			start_ext_halt;
   wire			adv_ir;
   wire			imem_dma_if;
   wire			imem_stall;

   wire 		old_taken;
   wire		[4:0]	pc_sel;
   wire			wr_taken_h0;
   wire			wr_taken_h1;
   wire			set_taken_h0;
   wire			set_taken_h1;
   wire			clear_taken_h0;
   wire			clear_taken_h1;
   wire			reset_taken_h1;
   wire 		if_taken_target;
   wire 		if_taken_target_n;
   wire		[11:2]	old_br_addr;
   wire		[11:2]	old_br_addr_n;
   wire			wr_br_addr;
   wire			pc_wr_en;
   wire			pc_wr_en_h0;
   wire			pc_wr_en_h1;

   wire 		old_target_pending;
   wire			old_target_pending_n;
   wire 		set_target_pending;
   wire 		clear_target_pending;
   wire 		wr_target_pending;
   wire			old_delay_pending;
   wire			old_delay_pending_n;
   wire 		set_delay_pending;
   wire 		clear_delay_pending;
   wire 		wr_delay_pending;

/* ********************************************************************** */
// Issue logic
 
   wire			adv_pcs;
   wire			adv_pcs_h0;
   wire		[11:3]  if_next_pc;		// IF stage
   wire		[11:2]	sav_pc;			// pc of saved instruction
   wire		[11:2]  int_halt_pc;
   wire		[63:0]	stalled_rd_inst;
   wire		[63:0]	muxed_rd_inst;
   wire		[31:0]	sav_inst;

   wire  	[11:3]  next_pc;		// RD stage
   wire		[11:2]	cur_rd_pc;
   wire		[11:2]	delay_pc;
   wire		[11:2]	link_pc;
   wire		[23:0]	rd_link_pc_delay_pc;	// RD stage

   wire			if_bubble;
   wire			if_other_bubble;
   wire			rd_other_bubble;
   wire			rd_other_bubble_tmp;
   wire 		if_next_is_target;
   wire 		rd_next_is_target;
   wire			target;
   wire			next_br_target;
   wire			even_target;		// target is 64-bit aligned
   wire			odd_target;		// target is not 64-bit aligned
   wire			delay_slot;
   wire			sav_br;
   wire			sav_su;
   wire			sav_vu;

   wire			fst_br;
   wire			snd_br;
   wire			fst_vu;	// first instruction of imem pair is VU type
   wire			snd_vu;	// second instruction of imem pair is VU type

   wire			next_target;
   wire			next_delay_slot;
   wire			next_sav_br;
   wire			next_sav_su;
   wire			next_sav_vu;

   wire		[4:0]	su_inst_sel;
   wire		[4:0]	vu_inst_sel;

   wire			sav_break;
   wire			fst_break;
   wire			fst_su_no_sav;
   wire			fst_vu_no_sav;
   wire			kill_su_issue_pre;
   wire			kill_vu_issue_pre;

   wire 		ex_break;
   wire 		issued_sav;
   wire 		issued_fst;
   wire 		issued_sec;

   wire 		prev_stalled;
   wire 		save_rd_inst;

   wire		[11:2]	pc_n; 
   wire		[11:2]	cur_rd_pc_n; 
   wire		[11:3]	next_pc_n; 
   wire		[23:0]	link_pc_delay_pc_n;
   wire			prev_stalled_n;
   wire		[63:0]	stalled_rd_inst_n; 
   wire		[31:0]	sav_inst_n; 
   wire			rd_next_is_target_n; 
   wire			imem_dma_if_n; 
   wire			rd_bubble; 
   wire			rd_bubble_n; 
   wire			rd_other_bubble_tmp_n; 
   wire			br_target; 
   wire			br_target_n; 
   wire			target_n; 
   wire			clr_state_n; 
   wire			sav_br_n;
   wire			sav_su_n;
   wire			sav_vu_n;
   wire			tmp_delay_slot_n;
   wire		[11:2]	sav_pc_n; 
   wire			ex_break_n; 


   pc_mux pc_mux(
	.reset_l		(reset_l),
	.clk			(clk),
	.if_next_pc		(if_next_pc),
	.old_br_addr		(old_br_addr),
	.old_taken		(old_taken),
	.br_addr		(br_addr),
	.pc_data_in		(pc_data_in),
	.pc_in_wr_en		(pc_in_wr_en),
	.taken			(taken),
	.int_halt_pc		(int_halt_pc),
	.halting		(halting),
	.pc_wr_en		(pc_wr_en),
	.pc			(pc)
   );

   assign if_next_pc = pc[11:3] + 1;

// Delay_pc is used for branch target calculations.  It is the pc of the 
// instruction following the branch.  If the branch instruction comes 
// from sav_inst (sav_br), then delay_pc is the pc of rd_inst.  If there 
// is no sav_br, but the first instruction of rd_inst is a branch (fst_br), 
// the delay_pc is the pc of the second instruction in rd_inst.  Finally, 
// if there is no sav_br and no fst_br, but the second instruction in rd_inst 
// is a branch, then delay_pc is the pc of the next sequential imem access 
// after rd_inst.  If there is no branch in sight, delay_pc is a don't care.

// Link_pc is the link address used for bxx_al and jalx.  It is the pc of 
// the second sequential instruction following the branch.  If the branch 
// instruction comes from sav_inst (sav_br), then link_pc is the pc of the 
// second instruction in rd_inst.  If there is no sav_br, but the first 
// instruction of rd_inst is a branch (fst_br), the link_pc is the pc of 
// the next sequential imem access after rd_inst.  Finally, if there is no 
// sav_br and no fst_br, but the second instruction in rd_inst is a branch,
// then link_pc is the pc of the second instruction in the  next sequential 
// imem access after rd_inst.  If there is no branch in sight, link_pc is a 
// don't care.

// *** This use of adv_pcs should be adv_ir ???:
   spasdffen_10_0 cur_pc_ff (cur_rd_pc, cur_rd_pc_n, pc, adv_pcs, clk, 1'b1);
// *** Perhaps this one could be, too:
   spasdffen_9_0 su_ir_pc_ff (next_pc, next_pc_n, if_next_pc, adv_pcs, clk, 1'b1);
   assign delay_pc = 
			 sav_br ? {cur_rd_pc[11:3], 1'b0} : 
			 fst_br ? {cur_rd_pc[11:3], 1'b1} : 
	    	     /* snd_br */ {next_pc, 1'b0};
   assign link_pc = 
			 sav_br ? {cur_rd_pc[11:3], 1'b1} : 
			 fst_br ? {next_pc, 1'b0} : 
		     /* snd_br */ {next_pc, 1'b1};
   assign rd_link_pc_delay_pc = {link_pc, 2'b0, delay_pc, 2'b0};
   spasdff_24_0 su_re_l_d_pc_ff (link_pc_delay_pc,link_pc_delay_pc_n,rd_link_pc_delay_pc,clk,1'b1);

/*
  Bubble generation: if pc_sel == 0010, there is a branch in EX, the branch 
  delay slot is in RD, and the instruction sequentially following the delay 
  slot is in IF.  The instructions in IF have to be killed.  (Also, only one 
  RD instruction is issued.)  This is difficult 
  in IF, because the IR flip-flop is included in the imem module.  So we wait 
  one cycle, then do it in RD.  We pipe pc_sel to the next cycle ( *** should 
  this be conditional on adv_ir?  Is adv_ir guaranteed to be 1 at this point?)
   and, conditional on it, kill the instruction now in RD.
*/

   assign fst_vu = prev_stalled ? (stalled_rd_inst[63:57] == 7'h25) : 
				  (rd_inst[63:57] == 7'h25);
   assign snd_vu = prev_stalled ? (stalled_rd_inst[31:25] == 7'h25) : 
				  (rd_inst[31:25] == 7'h25);
   assign fst_br = !odd_target && (
	(muxed_rd_inst[63:60] == 4'b0001) || 
	(muxed_rd_inst[63:59] == 5'b00001) || 
	(muxed_rd_inst[63:58] == 6'b000001) || 
      	((muxed_rd_inst[63:58]==6'b000000) && (muxed_rd_inst[35:33]==3'b100)));
   assign snd_br = 
	(muxed_rd_inst[31:28] == 4'b0001) || 
	(muxed_rd_inst[31:27] == 5'b00001) || 
	(muxed_rd_inst[31:26] == 6'b000001) || 
	((muxed_rd_inst[31:26]==6'b000000) && (muxed_rd_inst[3:1]==3'b100));

/* ***************************************************************** */
// Moved from suctl for timing reasons


   // Set a flag indicating that the next instruction to be executed is 
   // a delay slot instruction.
// Don't need rd_bubble, because it can't be a branch bubble *and* delay slot:
   assign set_delay_pending = delay_slot && kill_re;
   // Clear delay_pending when the delay slot instruction gets   *issued* 
   assign clear_delay_pending = !kill_re;
   assign wr_delay_pending = set_delay_pending || clear_delay_pending; 
   spasdffen_1_0 su_delpnd_ff (old_delay_pending,old_delay_pending_n, set_delay_pending, wr_delay_pending, clk, reset_l);

   // Set a flag indicating that the next instruction to be issued is a branch 
   // target.
   assign set_target_pending = (br_target || rd_bubble) && kill_re;
   assign clear_target_pending = !kill_re;
   assign wr_target_pending = set_target_pending || clear_target_pending; 
   spasdffen_1_0 su_tarpnd_ff (old_target_pending,old_target_pending_n, set_target_pending, wr_target_pending, clk, reset_l);

/*
   If there is a taken branch (pc_sel[2 or 3]) but adv_ir is deasserted, we 
   have to latch both taken and the branch address until adv_ir is next 
   asserted and the pc ff can be loaded.  Old_br_addr implements the address 
   latch; taken is latched in suctl.
*/

   assign wr_br_addr = taken && (!pc_wr_en || halting);
   spasdffen_10_0 is_br_addr_ff (old_br_addr, old_br_addr_n, br_addr,wr_br_addr,clk,reset_l);

   // Set a flag indicating that a branch condition has been met but the 
   // pc hasn't yet been loaded with the target pc, because there's a halt
   // condition or no pc write enable.
   // !clear_taken is because the halt pc can be loaded with the target 
   // address in the "taken" cycle.

/*
Original version:
   assign set_taken = (taken && !clear_taken && (!pc_wr_en || halting)) || reset_taken;
   // Clear old_taken when the target pc gets loaded into the pc:
   // pc <- taken || pc <- old_taken || pc <- halt_pc && halt_pc = target addr
   // pc_sel[2] || pc_sel[3] || (pc_sel[1] && )
   assign clear_taken = !reset_taken && pc_wr_en &&     // reset_taken should be impossible here
        (pc_sel[2] || pc_sel[3] || 
            (pc_sel[1] && (
                (!(delay_slot && kill_re) && (rd_bubble || (old_target_pending && !br_target))) ||
                (delay_slot && !kill_re && taken) || 
                (delay_slot && !kill_re && old_taken)
        )));
   // This addresses the situation where (following a halted state) a delay
   // slot instruction is in RD but is unable to issue, the branch target is 
   // in IF, and halting is asserted again.
   spasdffen_1_0 is_clr_taken_ff (if_taken_target, if_taken_target_n, clear_taken, pc_wr_en, clk, reset_l);
   assign reset_taken = delay_slot && kill_re && if_taken_target && halting;
   assign wr_taken = set_taken || clear_taken; 
   spasdffen_1_0 is_taken_ff (old_taken,old_taken_n, set_taken, wr_taken, clk, reset_l);



*/
   // Halting = 0 version
   // Enable pc write with pc input or int_halt_pc or "normal" next pc.

// assign adv_pcs = adv_ir && (!imem_stall || pc_sel[2] || pc_sel[3]);
   assign adv_pcs_h0 = adv_ir && (!imem_stall || (!pc_in_wr_en && taken) || (!pc_in_wr_en && !taken && old_taken));
   assign pc_wr_en_h0 = 
	pc_in_wr_en ||	(adv_pcs_h0 && !halt && !imem_dma_if);

   assign set_taken_h0 = taken && !clear_taken_h0 && !pc_wr_en_h0;
   // Clear old_taken when the target pc gets loaded into the pc:
   // pc <- taken || pc <- old_taken || pc <- halt_pc && halt_pc = target addr
   // pc_sel[2] || pc_sel[3] || (pc_sel[1] && )

   // It's possible to reduce this w.r.t. pc_in_wr_en term in pc_wr_en_h0:
   assign clear_taken_h0 = pc_wr_en_h0 && (!pc_in_wr_en && (taken || old_taken));
   // This addresses the situation where (following a halted state) a delay
   // slot instruction is in RD but is unable to issue, the branch target is 
   // in IF, and halting is asserted again.
   assign wr_taken_h0 = (taken && !pc_wr_en_h0) || clear_taken_h0; 	// set_taken || clear_taken

// Halting = 1 version.
   // Enable pc write with pc input or int_halt_pc or "normal" next pc.
   // assign pc_wr_en_h1 = 1'b1;

   assign set_taken_h1 = (taken && !clear_taken_h1) || reset_taken_h1;
   // Clear old_taken when the target pc gets loaded into the pc:
   // pc <- taken || pc <- old_taken || pc <- halt_pc && halt_pc = target addr
   // pc_sel[2] || pc_sel[3] || (pc_sel[1] && )
   assign clear_taken_h1 = !reset_taken_h1 && 	// reset_taken should be impossible here
	    !pc_in_wr_en && (
	    	(!(delay_slot && kill_re) && (rd_bubble || (old_target_pending && !br_target))) ||
     	    	(delay_slot && !kill_re && taken) || 
     	    	(delay_slot && !kill_re && old_taken)
        	);
   // This addresses the situation where (following a halted state) a delay
   // slot instruction is in RD but is unable to issue, the branch target is 
   // in IF, and halting is asserted again.
   assign reset_taken_h1 = delay_slot && kill_re && if_taken_target;
   assign wr_taken_h1 = taken || reset_taken_h1 || clear_taken_h1; // set_taken || clear_taken

   mx21d1h mx_clr_taken (.z(clear_taken), .i0(clear_taken_h0), .i1(clear_taken_h1), .s(halting));
   mx21d1h mx_set_taken (.z(set_taken), .i0(set_taken_h0), .i1(set_taken_h1), .s(halting));
   mx21d1h mx_wr_taken (.z(wr_taken), .i0(wr_taken_h0), .i1(wr_taken_h1), .s(halting));
   spasdffen_1_0 is_clr_taken_ff (if_taken_target, if_taken_target_n, clear_taken, pc_wr_en, clk, reset_l);
   spasdffen_1_0 is_taken_ff (old_taken,old_taken_n, set_taken, wr_taken, clk, reset_l);
   // Next PC Selection

   assign pc_sel[0] = pc_in_wr_en;		// pc gets  pc_data_in
   assign pc_sel[1] = !pc_in_wr_en && halting;	// pc gets int_halt_pc
   assign pc_sel[2] = !pc_in_wr_en && !halting && taken;
   assign pc_sel[3] = !pc_in_wr_en && !halting && !taken && old_taken;
   assign pc_sel[4] = !pc_in_wr_en && !halting && !taken && !old_taken;


/* ***************************************************************** */
// Halt sets if_bubble, therefore clearing all of this state during the 
// following cycle:
// *** No, it doesn't.  To force this, should "halting" also go into 
// *** next_delay_slot and next_target?
   assign odd_target = target && cur_rd_pc[2];
   assign even_target = target && !cur_rd_pc[2];
// *** Is this true in the presence of stalls, etc.? :
   assign next_br_target = rd_bubble || rd_next_is_target || 
	(old_target_pending && !clear_target_pending);
   assign next_target = rd_other_bubble || 
	(old_target_pending && !(target && !kill_re));
   // Next_delay_slot: there's a branch available to issue and it will issue.
   assign next_delay_slot = 
		!kill_re && !rd_other_bubble && (sav_br || 
		(fst_br && !sav_su && !sav_vu) ||
		(fst_br && sav_vu && !delay_slot && !kill_su_issue) ||
		(snd_br && odd_target) || 
		(snd_br && fst_vu && !odd_target && 
			!sav_su && !sav_vu && !delay_slot && !kill_su_issue));
// *** check use of !delay_slot in next_sav_br, next_sav_su, next_sav_vu
// *** next_br_target and rd_bubble are somewhat redundant in next_sav_xx
// *** remove redundant !odd target in next_sav_xx clauses.
   assign next_sav_br = !next_br_target && !odd_target && !halting && !rd_other_bubble && 
	!(delay_slot && (taken || old_taken)) &&  // = 2nd_br && next_sav_su;
        ((!fst_vu && snd_br && !odd_target && !sav_su && !sav_vu) || 
	    (!fst_vu && snd_br && !odd_target && !sav_su && 
		!delay_slot && sav_vu && !kill_su_issue) || 
	    (fst_vu && snd_br && delay_slot && !sav_su && !sav_vu) ||
	    (fst_vu&& snd_br&& !delay_slot && !sav_br && sav_su && !kill_vu_issue) ||
	    (fst_vu && snd_br && !odd_target && !delay_slot && 
		!sav_su && !sav_vu && kill_su_issue));
   assign next_sav_su = !next_br_target && !odd_target && !halting && !rd_other_bubble && 
	!(delay_slot && (taken || old_taken)) && 
	((!fst_vu && !snd_vu && !odd_target && !sav_su && !sav_vu) || 
	    (!fst_vu && !snd_vu && !odd_target && !sav_su && 
		!delay_slot && sav_vu && !kill_su_issue) || 
	    (fst_vu && !snd_vu && delay_slot && !sav_su && !sav_vu) ||
	    (fst_vu && !snd_vu && !delay_slot && !sav_br && sav_su && 
		!kill_vu_issue) ||
	    (fst_vu && !snd_vu && !odd_target && !delay_slot && 
		!sav_su && !sav_vu && kill_su_issue));

   assign next_sav_vu = !next_br_target && !odd_target && !halting && !rd_other_bubble && 
	!(delay_slot && (taken || old_taken)) && 
	((fst_vu && snd_vu && !odd_target && !sav_vu && !sav_su) || 
	    (fst_vu && snd_vu && !odd_target && !sav_vu && 
		!delay_slot && !sav_br && sav_su && !kill_vu_issue) || 
            (!fst_vu && snd_vu && delay_slot && !sav_su && !sav_vu) ||
	    (!fst_vu && snd_vu && !delay_slot && sav_vu && !kill_su_issue) ||
    (/* !fst_vu && */ snd_vu && !delay_slot && !sav_su && !sav_vu && fst_br) ||
	    (!fst_vu && snd_vu && !odd_target && !delay_slot && 
		!sav_su && !sav_vu && kill_vu_issue));

/* 
The enable on the IMem output FF is the same signal as chip select, which
is required to be valid about 1 ns before the *falling* edge of the clock.
We would like to use this FF to hold stalled instructions, but it's 
impossible to produce the stall signal (adv_ir) in time.  Therefore we 
create this side FF to hold instructions which should have been stalled, 
and add a leg to the su_inst_sel and vu_inst_sel muxes to choose the stalled
instruction.
*/

/* move should_have_stalled logic from suctl level to here -- Gulbin */

wire reset_l_lat;
wire reset_l_lat_n;
wire imem_chip_sel;

spasdff_1_0 su_reset_ff (reset_l_lat, reset_l_lat_n, reset_l, clk, 1'b1);
assign imem_chip_sel = !reset_l_lat || imem_dma_if || !halt;

wire pc_sel_2or3 = !pc_in_wr_en && (taken || old_taken);	// && !halting, added below
assign should_have_stalled =
    (imem_chip_sel && !imem_dma_if && !adv_ir) ||
    (imem_chip_sel && !imem_dma_if && imem_stall && !halting && !pc_sel_2or3) ;

spasdff_1_0_h prev_imem_stall_ff (prev_stalled, prev_stalled_n, should_have_stalled, clk, reset_l);
assign save_rd_inst = should_have_stalled && !prev_stalled;
spasdffen_64_h rd_inst_ff (stalled_rd_inst, stalled_rd_inst_n, rd_inst, save_rd_inst, clk);
// assign muxed_rd_inst = prev_stalled ? stalled_rd_inst : rd_inst;
muxed_inst muxed_inst (clk, reset_l, should_have_stalled, stalled_rd_inst, rd_inst, muxed_rd_inst);

   wire				fst_rd_vu;
   wire				fst_st_vu;

   assign fst_rd_vu = (rd_inst[63:57] == 7'h25);


   wire	fst_rd_vu_custom;
   wire not_fst_vu_not_odd;
   wire [5:0] su_inst_sel_enc;	// Bit [1] is duplicated in bit [5:3] for load reasons.

   spasdffen_1_0 fst_st_vu_ff (fst_st_vu, fst_st_vu_n, fst_rd_vu, save_rd_inst, clk, reset_l);

   su_inst_unit su_inst_unit (
	.clk			(clk),
	.reset_l		(reset_l), 
	.should_have_stalled	(should_have_stalled), 
	.sav_su_n		(sav_su_n),
	.rd_inst		(rd_inst), 
	.stalled_rd_inst	(stalled_rd_inst), 
	.sav_inst		(sav_inst), 
	.cur_rd_pc2		(cur_rd_pc[2]), 
	.target			(target), 
	.fst_st_vu		(fst_st_vu), 
	.fst_st_vu_n		(fst_st_vu_n), 
	.su_inst		(su_inst), 
	.fst_rd_vu_custom	(fst_rd_vu_custom), 
	.su_inst_sel_enc	(su_inst_sel_enc)
   );


   assign su_inst_sel[0] = sav_su;
   assign su_inst_sel[1] = !prev_stalled && !sav_su && !fst_rd_vu_custom && !odd_target;
   assign su_inst_sel[2] = !prev_stalled && !sav_su && (fst_rd_vu || odd_target);
   assign su_inst_sel[3] = prev_stalled && !sav_su && !fst_st_vu  && !odd_target;
   assign su_inst_sel[4] = prev_stalled && !sav_su && (fst_st_vu || odd_target);

   wire no_su_inst = (vu_inst_sel[0] && (su_inst_sel[1] || su_inst_sel[3]) && delay_slot) ||
	((vu_inst_sel[1] || vu_inst_sel[3]) && (su_inst_sel[2] || su_inst_sel[4]) && delay_slot) ||
	((su_inst_sel[2] || su_inst_sel[4]) && snd_vu) || 
	(vu_inst_sel[0] && (su_inst_sel[2] || su_inst_sel[4]));		// skipped one


   vu_inst_unit vu_inst_unit (
	.clk			(clk),
	.reset_l		(reset_l), 
	.should_have_stalled	(should_have_stalled), 
	.sav_vu_n		(sav_vu_n),
	.rd_inst		(rd_inst), 
	.stalled_rd_inst	(stalled_rd_inst), 
	.sav_inst		(sav_inst), 
	.cur_rd_pc2		(cur_rd_pc[2]), 
	.target			(target), 
	.fst_st_vu		(fst_st_vu), 
	.fst_st_vu_n		(fst_st_vu_n), 
	.vu_inst		(vu_inst)
   );

   assign vu_inst_sel[0] = sav_vu;
   assign vu_inst_sel[1] = !prev_stalled && !sav_vu && fst_rd_vu_custom && !odd_target;
   assign vu_inst_sel[2] = !prev_stalled && !sav_vu && (!fst_rd_vu || odd_target);
   assign vu_inst_sel[3] = prev_stalled && !sav_vu && fst_st_vu && !odd_target;
   assign vu_inst_sel[4] = prev_stalled && !sav_vu && (!fst_st_vu || odd_target);
								
   wire no_vu_inst = (su_inst_sel[0] && (vu_inst_sel[1] || vu_inst_sel[3]) && (delay_slot || sav_br || sav_break)) ||
	((su_inst_sel[1] || su_inst_sel[3]) && (vu_inst_sel[2] || vu_inst_sel[4]) && (delay_slot || fst_br || fst_break)) ||
	((vu_inst_sel[2] || vu_inst_sel[4]) && !snd_vu) || 
	(su_inst_sel[0] && (vu_inst_sel[2] || vu_inst_sel[4]));		// skipped one

   // Same mux routine as for the su_inst mux, except this is to 
   // determine whether the su_inst is a store transpose.

   wire rd_xpose_fst;
   wire rd_xpose_snd;
   wire st_xpose_fst, st_xpose_fst_n;
   wire st_xpose_snd, st_xpose_snd_n;
   wire muxed_sav_xp;
   wire sav_xpose, sav_xpose_n;
   wire xpose_1_a;
   wire xpose_1_b;
   wire xpose_1_c;
   wire xpose_1_d;
   wire xpose_2_a;
   wire xpose_2_b;
   wire st_xpose_unbuf;

   assign rd_xpose_snd = rd_inst[31] && (rd_inst[14:11]==4'b1011);
   assign rd_xpose_fst = rd_inst[63] && (rd_inst[46:43]==4'b1011);
   spasdffen_1_0 fst_xp_vu_ff (st_xpose_snd, st_xpose_snd_n, rd_xpose_snd, save_rd_inst, clk, reset_l);
   spasdffen_1_0 snd_xp_vu_ff (st_xpose_fst, st_xpose_fst_n, rd_xpose_fst, save_rd_inst, clk, reset_l);
   assign muxed_sav_xp =prev_stalled ? st_xpose_snd : rd_xpose_snd;
   spasdffen_1_0 su_sav_xp_ff (sav_xpose, sav_xpose_n, muxed_sav_xp,adv_ir, clk,reset_l);

   mx21d1h mx_xpose_1_a (.i0(rd_xpose_snd), .i1(st_xpose_snd), .s(su_inst_sel_enc[1]), .z(xpose_1_a));
   mx21d1h mx_xpose_1_b (.i0(rd_xpose_fst), .i1(st_xpose_snd), .s(su_inst_sel_enc[3]), .z(xpose_1_b));
   mx21d1h mx_xpose_1_c (.i0(st_xpose_fst), .i1(sav_xpose), .s(su_inst_sel_enc[4]), .z(xpose_1_c));
   mx21d1h mx_xpose_1_d (.i0(st_xpose_fst), .i1(sav_xpose), .s(su_inst_sel_enc[5]), .z(xpose_1_d));
   mx21d1h mx_xpose_2_a (.i0(xpose_1_a), .i1(xpose_1_c), .s(su_inst_sel_enc[2]), .z(xpose_2_a));
   mx21d1h mx_xpose_2_b (.i0(xpose_1_b), .i1(xpose_1_d), .s(su_inst_sel_enc[2]), .z(xpose_2_b));
   mx21d1h mx_xpose_3_a (.i0(xpose_2_a), .i1(xpose_2_b), .s(su_inst_sel_enc[0]), .z(st_xpose_unbuf));
   ni01d5 st_xpose_buf (.i(st_xpose_unbuf), .z(store_xpose_rd));

/*
000: rd_xpose_snd	[31:0]
001: rd_xpose_fst	[63:32]
010: st_xpose_snd	[31:0]
011: st_xpose_snd	[31:0]
100: st_xpose_fst	[63:32]
101: st_xpose_fst	[63:32]
110: sav_xpose
111: sav_xpose
*/

   wire [31:0] muxed_sav_inst;
   assign muxed_sav_inst =prev_stalled ? stalled_rd_inst[31:0] : rd_inst[31:0];
   spasdffen_32_0 su_sav_inst_ff (sav_inst, sav_inst_n, muxed_sav_inst,adv_ir, clk,reset_l);

   assign fst_su_no_sav = !sav_su && !sav_vu && (su_inst_sel[1]||su_inst_sel[3]);
   assign fst_vu_no_sav = !sav_su && !sav_vu && (vu_inst_sel[1]||vu_inst_sel[3]);

   // If delay slot is stalled one cycle, don't want to kill it.  Hence, 
   // (rd_bubble && !delay_slot).   

   assign kill_su_issue_pre = rd_other_bubble_tmp || (rd_bubble && !delay_slot) || no_su_inst;
   assign kill_vu_issue_pre = rd_other_bubble_tmp || (rd_bubble && !delay_slot) || no_vu_inst;

   kill_unit kill_unit (sav_inst, muxed_rd_inst[63:32], muxed_rd_inst[31:0], 
	sav_su, sav_vu, fst_su_no_sav, fst_vu_no_sav, 
	single_step, kill_su_issue_pre, kill_vu_issue_pre, 
	kill_su_issue, kill_vu_issue);

   assign su_nop_debug = (kill_su_issue || kill_re);
   assign vu_nop_debug = (kill_vu_issue || kill_re);

   assign imem_stall = !rd_bubble && 
	((sav_su && (!fst_vu || delay_slot || sav_br || kill_vu_issue)) || 
	(sav_vu && (fst_vu || delay_slot || kill_su_issue)));
	// = (sav_su && !(vu_inst_sel[1] || vu_inst_sel[3])) || 
	// (sav_vu && (!su_inst_sel[1] || su_inst_sel[3]));

   // Only need bubble when there is no interruption between the taken 
   // branch and the target instruction.  pc_sel[2] indicates there is 
   // a taken branch in EX and the target pc will enter IF in the next
   // cycle.

   assign if_bubble = (pc_sel[2] || pc_sel[3]) && pc_wr_en;

   // These are used to figure out when we're at the target of a branch even 
   // though there was no rd_bubble.
   assign if_next_is_target = pc_sel[3] && pc_wr_en;
   spasdffen_1_0 is_ir_next_tar_ff (rd_next_is_target, rd_next_is_target_n, if_next_is_target, adv_ir, clk, reset_l);

// if pc is target pc = prev pc_wr_en && prev_pc_mux=
   spasdff_1_0 su_pifif_dma_ff(imem_dma_if, imem_dma_if_n, imem_dma_pif, clk, reset_l);
   assign if_other_bubble = halt || (imem_dma_if & !imem_dma_pif);

   spasdffen_1_0 su_ir_bubble_ff (rd_bubble, rd_bubble_n, if_bubble, adv_ir,clk, reset_l);
   spasdff_1_0 su_ir_obubble_ff (rd_other_bubble_tmp, rd_other_bubble_tmp_n, if_other_bubble,clk,reset_l);
   spasdffen_1_0 su_btarget_ff (br_target, br_target_n, next_br_target,!kill_re,clk, reset_l);
   spasdffen_1_0 su_target_ff (target, target_n, next_target, adv_ir, clk, reset_l);

   wire tmp_delay_slot;
   spasdff_1_0_h su_sv_br_ff (			// rigged high-perf ff w/ en
	sav_br, sav_br_n,
	((!kill_re||halting) ? next_sav_br : sav_br),
	clk, reset_l);
   spasdff_1_0_h su_sv_su_ff (			// rigged high-perf ff w/ en
	sav_su, sav_su_n,
	((!kill_re||halting) ? next_sav_su : sav_su),
	clk, reset_l);
   spasdff_1_0_h su_sv_vu_ff (			// rigged high-perf ff w/ en
	sav_vu, sav_vu_n,
	((!kill_re||halting) ? next_sav_vu : sav_vu), 
	clk, reset_l);
   spasdffen_1_0 su_del_slot_ff(tmp_delay_slot,tmp_delay_slot_n,next_delay_slot,adv_ir,clk,reset_l);

   assign delay_slot = tmp_delay_slot || old_delay_pending;

   assign rd_other_bubble = rd_other_bubble_tmp || rd_bubble;
   spasdffen_10_0 su_sav_pc_ff (sav_pc,sav_pc_n, {cur_rd_pc[11:3],1'b1},adv_ir,clk,1'b1);

   /*
   assign su_rd_pc_debug = 		// for debug only
	su_inst_sel[0] ? {sav_pc, 2'b00} :
	su_inst_sel[1] ? {cur_rd_pc[11:3], 3'b000} :
	su_inst_sel[2] ? {cur_rd_pc[11:3], 3'b100} :
	su_inst_sel[3] ? {cur_rd_pc[11:3], 3'b000} :
	su_inst_sel[4] ? {cur_rd_pc[11:3], 3'b100} :
			  12'b0;

   assign vu_rd_pc_debug = 		// for debug only
	vu_inst_sel[0] ? {sav_pc, 2'b00} :
	vu_inst_sel[1] ? {cur_rd_pc[11:3], 3'b000} :
	vu_inst_sel[2] ? {cur_rd_pc[11:3], 3'b100} :
	vu_inst_sel[3] ? {cur_rd_pc[11:3], 3'b000} :
	vu_inst_sel[4] ? {cur_rd_pc[11:3], 3'b100} :
			 12'b0;
   */

/* ********************************************************************** */
// Dual-issue hazards

   // Detect hazards (VU register and VU control register) between the two 
   // instructions that are otherwise expected to dual-issue.
   // *** This could be very bad, timing-wise.

   assign sav_break = (sav_inst[31:26]==6'b000000)&&(sav_inst[5:0]==6'b001101);
   assign fst_break = (muxed_rd_inst[63:58]==6'b000000)&&(muxed_rd_inst[37:32]==6'b001101);

   // For timing reasons, always single-issue "break" instruction.  This 
   // Makes it unnecessary to include vu register hazard conditions in 
   // rd_broke_k.

// When halt is deasserted, pc is pointing to the first instruction to execute
// and the rd_inst is garbage.  Therefore, when halt is deasserted, *don't* 
// issue an instruction in that cycle.  Wait til the next one.

// The PC is only written when the RSP is halted.  The pipe is empty,
// and cur_rd_pc, link_pc_delay_pc, and next_pc are don't cares (so it's
// ok to write them, too).

// *** What happens here if an instruction is issued but stalls in rd. 
// *** It should complete and be unaffected by stall.
// *** But this won't work for IMem DMA, where we have to get out of the way 
// *** in a fixed time (2 cycles) for DMA.  But DMA shouldn't be happening 
// *** where we're executing ... that's a software restriction. (Whether we're 
// *** halted or not?)

// *** IMem write: just stall everything, including rd_inst, and continue 
// *** when it's done.
// *** IMem read: assume we've already come to a graceful halt

   assign issued_sav =  (sav_su && !kill_su_issue) || 
			(sav_vu && !kill_vu_issue);
   assign issued_fst =			// issued first implies !odd_target 
	(((su_inst_sel[1] || su_inst_sel[3]) && !kill_su_issue) ||
	 ((vu_inst_sel[1] || vu_inst_sel[3]) && !kill_vu_issue));
   assign issued_sec = 
	(((su_inst_sel[2] || su_inst_sel[4]) && !kill_su_issue) ||
	 ((vu_inst_sel[2] || vu_inst_sel[4]) && !kill_vu_issue));

/* ******************************************************************* */
// Kill_re = 0
   wire [7:0] halt_sel_a;
   reg  [11:2] int_halt_pc_a_reg;
   wire  [11:2] int_halt_pc_a;

   assign halt_sel_a[0] = (halt_sel_a[2:1]==2'b0) && (rd_bubble || (old_target_pending && !br_target));
   assign halt_sel_a[1] = delay_slot && taken; 
   assign halt_sel_a[2] = delay_slot && !taken && old_taken;
   assign halt_sel_a[3] = (halt_sel_a[2:0]==3'b0) && (sav_su || sav_vu) && !issued_sav;
   assign halt_sel_a[4] = (halt_sel_a[2:0]==3'b0) && issued_sav && !issued_fst && !issued_sec && !odd_target;
   assign halt_sel_a[5] = (halt_sel_a[2:0]==3'b0) && issued_fst && !issued_sec;	// !odd_target implied by issued_fst
   assign halt_sel_a[6] = (halt_sel_a[2:0]==3'b0) && !issued_sec && odd_target;
   assign halt_sel_a[7] = (halt_sel_a[2:0]==3'b0) && issued_sec;

   always @(halt_sel_a or pc or sav_pc or cur_rd_pc or br_addr or old_br_addr) 
   begin
       case (1'b1) 			//synopsys parallel_case
           halt_sel_a[0] : int_halt_pc_a_reg = pc[11:2];
           halt_sel_a[1] : int_halt_pc_a_reg = br_addr[11:2];
           halt_sel_a[2] : int_halt_pc_a_reg = old_br_addr[11:2];
           halt_sel_a[3] : int_halt_pc_a_reg = sav_pc[11:2];
           halt_sel_a[4] : int_halt_pc_a_reg = {cur_rd_pc[11:3], 1'b0};
           halt_sel_a[5] : int_halt_pc_a_reg = {cur_rd_pc[11:3], 1'b1};
           halt_sel_a[6] : int_halt_pc_a_reg = {cur_rd_pc[11:3], 1'b1};
           halt_sel_a[7] : int_halt_pc_a_reg = {pc[11:3], 1'b0};
           default     : int_halt_pc_a_reg = {cur_rd_pc[11:3], 1'b0};	// first instruction, used for delay_slot && kill_re && !sav_xu
       endcase
   end
   assign int_halt_pc_a = int_halt_pc_a_reg;

/* *********************************************************************** */
// Kill_re = 1

   wire [7:0] halt_sel_b;
   reg  [11:2] int_halt_pc_b_reg;
   wire  [11:2] int_halt_pc_b;

   assign halt_sel_b[0] = (halt_sel_b[2:1]==2'b0) && !(delay_slot) && (rd_bubble || (old_target_pending && !br_target));
   assign halt_sel_b[1] = 0;
   assign halt_sel_b[2] = 0;
   assign halt_sel_b[3] = (halt_sel_b[2:0]==3'b0) && (sav_su || sav_vu);
   assign halt_sel_b[4] = 0;
   assign halt_sel_b[5] = 0;
   assign halt_sel_b[6] = (halt_sel_b[2:0]==3'b0) && odd_target;
   assign halt_sel_b[7] = 0;

   always @(halt_sel_b or pc or sav_pc or cur_rd_pc or br_addr or old_br_addr) 
   begin
       case (1'b1) 			//synopsys parallel_case
           halt_sel_b[0] : int_halt_pc_b_reg = pc[11:2];
           halt_sel_b[1] : int_halt_pc_b_reg = br_addr[11:2];
           halt_sel_b[2] : int_halt_pc_b_reg = old_br_addr[11:2];
           halt_sel_b[3] : int_halt_pc_b_reg = sav_pc[11:2];
           halt_sel_b[4] : int_halt_pc_b_reg = {cur_rd_pc[11:3], 1'b0};
           halt_sel_b[5] : int_halt_pc_b_reg = {cur_rd_pc[11:3], 1'b1};
           halt_sel_b[6] : int_halt_pc_b_reg = {cur_rd_pc[11:3], 1'b1};
           halt_sel_b[7] : int_halt_pc_b_reg = {pc[11:3], 1'b0};
           default     : int_halt_pc_b_reg = {cur_rd_pc[11:3], 1'b0};	// first instruction, used for delay_slot && kill_re && !sav_xu
       endcase
   end
   assign int_halt_pc_b = int_halt_pc_b_reg;
/* *********************************************************************** */
   mx2h_10 halt_pc_mux (.i0(int_halt_pc_a), .i1(int_halt_pc_b), .s(kill_re), .z(int_halt_pc));

   // *** There is an identical ex_break ff in suctl:
   spasdff_1_0 is_re_break_ff (ex_break, ex_break_n, set_broke, clk, reset_l);

   // Enable pc write with pc input or int_halt_pc or "normal" next pc.
   assign pc_wr_en = 
	pc_in_wr_en ||				// external write
	halting || 
	(adv_pcs && !halt && !imem_dma_if); 	// normal condition

   // Advance unless there are instructions that have to be executed in the
   // IR latch (imem_stall and not taking a branch).
   assign adv_pcs = adv_ir && (!imem_stall || pc_sel[2] || pc_sel[3]);

endmodule

module inst_mux_new(z, i0, i1, i2, i3, i4, i5, i6, i7, s);
input [31:0] i0, i1, i2, i3, i4, i5, i6, i7;
input [5:0] s;
output [31:0] z;

wire [31:0] inst_1_a, inst_1_b, inst_1_c, inst_1_d;
wire [31:0] inst_2_a, inst_2_b;
wire [31:0] unbufz;

mx2h_32 mx_level_1_a (.i0(i0), .i1(i2), .s(s[1]), .z(inst_1_a));
mx2h_32 mx_level_1_b (.i0(i1), .i1(i3), .s(s[3]), .z(inst_1_b));
mx2h_32 mx_level_1_c (.i0(i4), .i1(i6), .s(s[4]), .z(inst_1_c));
mx2h_32 mx_level_1_d (.i0(i5), .i1(i7), .s(s[5]), .z(inst_1_d));

mx2h_32 mx_level_2_a (.i0(inst_1_a), .i1(inst_1_c), .s(s[2]), .z(inst_2_a));
mx2h_32 mx_level_2_b (.i0(inst_1_b), .i1(inst_1_d), .s(s[2]), .z(inst_2_b));

mx2h_32 mx_level_3_a (.i0(inst_2_a), .i1(inst_2_b), .s(s[0]), .z(unbufz));

ni01d7 ub_0(.z(z[0]), .i(unbufz[0]));
ni01d7 ub_1(.z(z[1]), .i(unbufz[1]));
ni01d7 ub_2(.z(z[2]), .i(unbufz[2]));
ni01d7 ub_3(.z(z[3]), .i(unbufz[3]));
ni01d7 ub_4(.z(z[4]), .i(unbufz[4]));
ni01d7 ub_5(.z(z[5]), .i(unbufz[5]));
ni01d7 ub_6(.z(z[6]), .i(unbufz[6]));
ni01d7 ub_7(.z(z[7]), .i(unbufz[7]));
ni01d7 ub_8(.z(z[8]), .i(unbufz[8]));
ni01d7 ub_9(.z(z[9]), .i(unbufz[9]));
ni01d7 ub_10(.z(z[10]), .i(unbufz[10]));
ni01d7 ub_11(.z(z[11]), .i(unbufz[11]));
ni01d7 ub_12(.z(z[12]), .i(unbufz[12]));
ni01d7 ub_13(.z(z[13]), .i(unbufz[13]));
ni01d7 ub_14(.z(z[14]), .i(unbufz[14]));
ni01d7 ub_15(.z(z[15]), .i(unbufz[15]));
ni01d7 ub_16(.z(z[16]), .i(unbufz[16]));
ni01d7 ub_17(.z(z[17]), .i(unbufz[17]));
ni01d7 ub_18(.z(z[18]), .i(unbufz[18]));
ni01d7 ub_19(.z(z[19]), .i(unbufz[19]));
ni01d7 ub_20(.z(z[20]), .i(unbufz[20]));
ni01d7 ub_21(.z(z[21]), .i(unbufz[21]));
ni01d7 ub_22(.z(z[22]), .i(unbufz[22]));
ni01d7 ub_23(.z(z[23]), .i(unbufz[23]));
ni01d7 ub_24(.z(z[24]), .i(unbufz[24]));
ni01d7 ub_25(.z(z[25]), .i(unbufz[25]));
ni01d7 ub_26(.z(z[26]), .i(unbufz[26]));
ni01d7 ub_27(.z(z[27]), .i(unbufz[27]));
ni01d7 ub_28(.z(z[28]), .i(unbufz[28]));
ni01d7 ub_29(.z(z[29]), .i(unbufz[29]));
ni01d7 ub_30(.z(z[30]), .i(unbufz[30]));
ni01d7 ub_31(.z(z[31]), .i(unbufz[31]));

endmodule


module mx2h_32 (i0, i1, s, z);

input [31:0] i0;
input [31:0] i1;
input s;
output [31:0] z;

wire sa, sb, sc, sd;

ni01d5 u_sa_2(.z(sa), .i(s));
ni01d5 u_sb_2(.z(sb), .i(s));
ni01d5 u_sc_2(.z(sc), .i(s));
ni01d5 u_sd_2(.z(sd), .i(s));

mx21d1h u_00(.z(z[ 0]), .i0(i0[ 0]), .i1(i1[ 0]), .s(sa));
mx21d1h u_01(.z(z[ 1]), .i0(i0[ 1]), .i1(i1[ 1]), .s(sa));
mx21d1h u_02(.z(z[ 2]), .i0(i0[ 2]), .i1(i1[ 2]), .s(sa));
mx21d1h u_03(.z(z[ 3]), .i0(i0[ 3]), .i1(i1[ 3]), .s(sa));
mx21d1h u_04(.z(z[ 4]), .i0(i0[ 4]), .i1(i1[ 4]), .s(sa));
mx21d1h u_05(.z(z[ 5]), .i0(i0[ 5]), .i1(i1[ 5]), .s(sa));
mx21d1h u_06(.z(z[ 6]), .i0(i0[ 6]), .i1(i1[ 6]), .s(sa));
mx21d1h u_07(.z(z[ 7]), .i0(i0[ 7]), .i1(i1[ 7]), .s(sa));

mx21d1h u_08(.z(z[ 8]), .i0(i0[ 8]), .i1(i1[ 8]), .s(sb));
mx21d1h u_09(.z(z[ 9]), .i0(i0[ 9]), .i1(i1[ 9]), .s(sb));
mx21d1h u_10(.z(z[10]), .i0(i0[10]), .i1(i1[10]), .s(sb));
mx21d1h u_11(.z(z[11]), .i0(i0[11]), .i1(i1[11]), .s(sb));
mx21d1h u_12(.z(z[12]), .i0(i0[12]), .i1(i1[12]), .s(sb));
mx21d1h u_13(.z(z[13]), .i0(i0[13]), .i1(i1[13]), .s(sb));
mx21d1h u_14(.z(z[14]), .i0(i0[14]), .i1(i1[14]), .s(sb));
mx21d1h u_15(.z(z[15]), .i0(i0[15]), .i1(i1[15]), .s(sb));

mx21d1h u_16(.z(z[16]), .i0(i0[16]), .i1(i1[16]), .s(sc));
mx21d1h u_17(.z(z[17]), .i0(i0[17]), .i1(i1[17]), .s(sc));
mx21d1h u_18(.z(z[18]), .i0(i0[18]), .i1(i1[18]), .s(sc));
mx21d1h u_19(.z(z[19]), .i0(i0[19]), .i1(i1[19]), .s(sc));
mx21d1h u_20(.z(z[20]), .i0(i0[20]), .i1(i1[20]), .s(sc));
mx21d1h u_21(.z(z[21]), .i0(i0[21]), .i1(i1[21]), .s(sc));
mx21d1h u_22(.z(z[22]), .i0(i0[22]), .i1(i1[22]), .s(sc));
mx21d1h u_23(.z(z[23]), .i0(i0[23]), .i1(i1[23]), .s(sc));

mx21d1h u_24(.z(z[24]), .i0(i0[24]), .i1(i1[24]), .s(sd));
mx21d1h u_25(.z(z[25]), .i0(i0[25]), .i1(i1[25]), .s(sd));
mx21d1h u_26(.z(z[26]), .i0(i0[26]), .i1(i1[26]), .s(sd));
mx21d1h u_27(.z(z[27]), .i0(i0[27]), .i1(i1[27]), .s(sd));
mx21d1h u_28(.z(z[28]), .i0(i0[28]), .i1(i1[28]), .s(sd));
mx21d1h u_29(.z(z[29]), .i0(i0[29]), .i1(i1[29]), .s(sd));
mx21d1h u_30(.z(z[30]), .i0(i0[30]), .i1(i1[30]), .s(sd));
mx21d1h u_31(.z(z[31]), .i0(i0[31]), .i1(i1[31]), .s(sd));

endmodule

module mx2h_10 (i0, i1, s, z);

input [9:0] i0;
input [9:0] i1;
input s;
output [9:0] z;

ni01d5 u_sa_2(.z(sa), .i(s));
ni01d5 u_sb_2(.z(sb), .i(s));

mx21d1h u_00(.z(z[ 0]), .i0(i0[ 0]), .i1(i1[ 0]), .s(sa));
mx21d1h u_01(.z(z[ 1]), .i0(i0[ 1]), .i1(i1[ 1]), .s(sa));
mx21d1h u_02(.z(z[ 2]), .i0(i0[ 2]), .i1(i1[ 2]), .s(sa));
mx21d1h u_03(.z(z[ 3]), .i0(i0[ 3]), .i1(i1[ 3]), .s(sa));
mx21d1h u_04(.z(z[ 4]), .i0(i0[ 4]), .i1(i1[ 4]), .s(sa));

mx21d1h u_05(.z(z[ 5]), .i0(i0[ 5]), .i1(i1[ 5]), .s(sb));
mx21d1h u_06(.z(z[ 6]), .i0(i0[ 6]), .i1(i1[ 6]), .s(sb));
mx21d1h u_07(.z(z[ 7]), .i0(i0[ 7]), .i1(i1[ 7]), .s(sb));
mx21d1h u_08(.z(z[ 8]), .i0(i0[ 8]), .i1(i1[ 8]), .s(sb));
mx21d1h u_09(.z(z[ 9]), .i0(i0[ 9]), .i1(i1[ 9]), .s(sb));

endmodule

module su_inst_unit (clk, reset_l, should_have_stalled, sav_su_n, 
	rd_inst, stalled_rd_inst, sav_inst, cur_rd_pc2, target, 
	fst_st_vu, fst_st_vu_n, su_inst, fst_rd_vu_custom, su_inst_sel_enc);

   input		clk;
   input		reset_l;
   input		should_have_stalled;
   input		sav_su_n;
   input	[63:0] 	rd_inst;
   input	[63:0] 	stalled_rd_inst;
   input		cur_rd_pc2;
   input 	[31:0] 	sav_inst;
   input		target;
   input		fst_st_vu;
   input		fst_st_vu_n;

   output 	[31:0] 	su_inst;
   output 		fst_rd_vu_custom;
   output 	[5:0] 	su_inst_sel_enc;	// Bit [1] is duplicated in bit [5:3] for load reasons.

   wire local_prev_stalled;
   wire local_prev_stalled_n;
   wire rd_inst_62_l;
   wire rd_inst_59_l;
   wire rd_inst_57_l;
   wire	fst_rd_vu_custom;
   wire odd_target_custom;
   wire odd_target_custom_l;
   wire su_sel_enc_1a;
   wire su_sel_enc_2a;
   wire su_sel_enc_2b;

/*
   assign su_inst_sel_enc[0] = !fst_rd_vu && !odd_target;
   assign su_inst_sel_enc[1] = sav_su || (prev_stalled && (fst_st_vu || odd_target));
   assign su_inst_sel_enc[2] = sav_su || (prev_stalled && !fst_st_vu  && !odd_target);

   fst_st_vu || odd_target = xxx.  !(fst_st_vu || odd_target) = !fst_st_vu && !odd_target = !xxx.
   fst_rd_vu || odd_target = yyy.  !(fst_rd_vu || odd_target) = !fst_rd_vu && !odd_target = !yyy. 
   assign su_inst_sel_enc[0] = !yyy;
   assign su_inst_sel_enc[1] = sav_su || (prev_stalled && xxx);
   assign su_inst_sel_enc[2] = sav_su || (prev_stalled && !xxx);

   000: !sav_su && !prev_stalled && yyy 
   001: !sav_su && !prev_stalled && !yyy
   010: !sav_su && prev_stalled && xxx && yyy
   011: !sav_su && prev_stalled && xxx && !yyy
   100: !sav_su && prev_stalled && !xxx && yyy
   101: !sav_su && prev_stalled && !xxx && !yyy
   110: sav_su && yyy
   111: sav_su && !yyy
*/

   dfctnh is_su_loc_stall (.q(loc_prev_stalled), .qn(loc_prev_stalled_n), .d(should_have_stalled), .cp(clk), .cdn(reset_l)); 
   
   in01d1 in_rd_inst_62 (.i(rd_inst[62]), .zn(rd_inst_62_l));
   in01d1 in_rd_inst_59 (.i(rd_inst[59]), .zn(rd_inst_59_l));
   in01d1 in_rd_inst_57 (.i(rd_inst[57]), .zn(rd_inst_57_l));

   // odd_target and fst_rd_vu, custom version:
   an02d3 an_odd_tar (.a1(target), .a2(cur_rd_pc2), .z(odd_target_custom));
   nd02d3 nd_odd_tar (.a1(target), .a2(cur_rd_pc2), .zn(odd_target_custom_l));
   nr05d2 nr_fst_rd (.a1(rd_inst[63]), .a2(rd_inst_62_l), .a3(rd_inst[60]), .a4(rd_inst_59_l), .a5(rd_inst_57_l), .zn(fst_rd_vu_custom));
   nr02d3 nr_su_sel_enc_0 (.a1(fst_rd_vu_custom), .a2(odd_target_custom), .zn(su_inst_sel_enc[0]));

   nd02d2 nd_su_sel_enc_1a (.a1(loc_prev_stalled), .a2(fst_st_vu), .zn(su_sel_enc_1a));
   nd02d2 nd_su_sel_enc_1b (.a1(loc_prev_stalled), .a2(odd_target_custom), .zn(su_sel_enc_1b));
   nd03d2 nd_su_sel_enc_1 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[1]));
   nd03d2 nd_su_sel_enc_3 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[3]));
   nd03d2 nd_su_sel_enc_4 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[4]));
   nd03d2 nd_su_sel_enc_5 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[5]));

   nd03d2 nd_su_sel_enc_2a (.a1(loc_prev_stalled), .a2(fst_st_vu_n), .a3(odd_target_custom_l), .zn(su_sel_enc_2a));
   nd02d3 nd_su_sel_enc_2 (.a1(su_sel_enc_2a), .a2(sav_su_n), .zn(su_inst_sel_enc[2]));

   inst_mux_new su_inst_mux(
	.z(su_inst), 
	.i0(rd_inst[31:0]), 
	.i1(rd_inst[63:32]), 
	.i2(stalled_rd_inst[31:0]), 
	.i3(stalled_rd_inst[31:0]), 
	.i4(stalled_rd_inst[63:32]), 
	.i5(stalled_rd_inst[63:32]), 
	.i6(sav_inst), 
	.i7(sav_inst), 
	.s(su_inst_sel_enc));

endmodule

module vu_inst_unit (clk, reset_l, should_have_stalled, sav_vu_n, 
	rd_inst, stalled_rd_inst, sav_inst, cur_rd_pc2, target, 
	fst_st_vu, fst_st_vu_n, vu_inst);

   input		clk;
   input		reset_l;
   input		should_have_stalled;
   input		sav_vu_n;
   input	[63:0] 	rd_inst;
   input	[63:0] 	stalled_rd_inst;
   input	[31:0] 	sav_inst;
   input	 	cur_rd_pc2;
   input		target;
   input		fst_st_vu;
   input		fst_st_vu_n;

   output 	[31:0] 	vu_inst;

   wire loc_prev_stalled;
   wire loc_prev_stalled_n;
   wire rd_inst_62_l;
   wire rd_inst_59_l;
   wire rd_inst_57_l;
   wire odd_target_custom;
   wire odd_target_custom_l;
   wire vu_sel_enc_1a;
   wire vu_sel_enc_2a;
   wire vu_sel_enc_2b;
   wire [5:0] vu_inst_sel_enc;	// Bit [1] is duplicated in bit [5:3] for load reasons.

/*
   assign vu_inst_sel_enc[0] = fst_rd_vu && !odd_target;
   assign vu_inst_sel_enc[1] = sav_vu || (prev_stalled && (!fst_st_vu || odd_target));
   assign vu_inst_sel_enc[2] = sav_vu || (prev_stalled && fst_st_vu  && !odd_target);

   !fst_st_vu || odd_target = aaa.  !(!fst_st_vu || odd_target) = fst_st_vu && !odd_target = !aaa.
   !fst_rd_vu || odd_target = bbb.  !(!fst_rd_vu || odd_target) = fst_rd_vu && !odd_target = !bbb.
   assign vu_inst_sel_enc[0] = !bbb;
   assign vu_inst_sel_enc[1] = sav_vu || (prev_stalled && aaa);
   assign vu_inst_sel_enc[2] = sav_vu || (prev_stalled && !aaa);

   000: !sav_vu && !prev_stalled && bbb
   001: !sav_vu && !prev_stalled && !bbb
   010: !sav_vu && prev_stalled && aaa && bbb 
   011: !sav_vu && prev_stalled && aaa && !bbb 
   100: !sav_vu && prev_stalled && !aaa && bbb 
   101: !sav_vu && prev_stalled && !aaa && !bbb 
   110: sav_vu && bbb 
   111: sav_vu && !bbb 
*/

   dfctnh is_vu_loc_stall (.q(loc_prev_stalled), .qn(loc_prev_stalled_n), .d(should_have_stalled), .cp(clk), .cdn(reset_l)); 

   in01d1 in_rd_inst_62 (.i(rd_inst[62]), .zn(rd_inst_62_l));
   in01d1 in_rd_inst_59 (.i(rd_inst[59]), .zn(rd_inst_59_l));
   in01d1 in_rd_inst_57 (.i(rd_inst[57]), .zn(rd_inst_57_l));

   an02d3 an_odd_tar (.a1(target), .a2(cur_rd_pc2), .z(odd_target_custom));
   nd02d3 nd_odd_tar (.a1(target), .a2(cur_rd_pc2), .zn(odd_target_custom_l));
   nr06d2 nr_vu_sel_enc_0 (.a1(rd_inst[63]), .a2(rd_inst_62_l), .a3(rd_inst[60]), .a4(rd_inst_59_l), .a5(rd_inst_57_l), .a6(odd_target_custom), .zn(vu_inst_sel_enc[0]));

   nd02d2 nd_vu_sel_enc_1a (.a1(loc_prev_stalled), .a2(fst_st_vu_n), .zn(vu_sel_enc_1a));
   nd02d2 nd_vu_sel_enc_1b (.a1(loc_prev_stalled), .a2(odd_target_custom), .zn(vu_sel_enc_1b));
   nd03d2 nd_vu_sel_enc_1 (.a1(vu_sel_enc_1a), .a2(vu_sel_enc_1b), .a3(sav_vu_n), .zn(vu_inst_sel_enc[1]));
   nd03d2 nd_vu_sel_enc_3 (.a1(vu_sel_enc_1a), .a2(vu_sel_enc_1b), .a3(sav_vu_n), .zn(vu_inst_sel_enc[3]));
   nd03d2 nd_vu_sel_enc_4 (.a1(vu_sel_enc_1a), .a2(vu_sel_enc_1b), .a3(sav_vu_n), .zn(vu_inst_sel_enc[4]));
   nd03d2 nd_vu_sel_enc_5 (.a1(vu_sel_enc_1a), .a2(vu_sel_enc_1b), .a3(sav_vu_n), .zn(vu_inst_sel_enc[5]));

   nd03d2 nd_vu_sel_enc_2a (.a1(loc_prev_stalled), .a2(fst_st_vu), .a3(odd_target_custom_l), .zn(vu_sel_enc_2a));
   nd02d3 nd_vu_sel_enc_2 (.a1(vu_sel_enc_2a), .a2(sav_vu_n), .zn(vu_inst_sel_enc[2]));

   inst_mux_new vu_inst_mux(
	.z(vu_inst), 
	.i0(rd_inst[31:0]), 
	.i1(rd_inst[63:32]), 
	.i2(stalled_rd_inst[31:0]), 
	.i3(stalled_rd_inst[31:0]), 
	.i4(stalled_rd_inst[63:32]), 
	.i5(stalled_rd_inst[63:32]), 
	.i6(sav_inst), 
	.i7(sav_inst), 
	.s(vu_inst_sel_enc));

endmodule

module pc_mux(reset_l, clk, if_next_pc, old_br_addr, old_taken, br_addr, 
	pc_data_in, pc_in_wr_en, taken, int_halt_pc, halting, 
	pc_wr_en, pc);

   input		reset_l;
   input		clk;
   input	[11:3]	if_next_pc;
   input	[11:2]	old_br_addr;
   input		old_taken;
   input	[11:2]	br_addr;
   input	[11:2]	pc_data_in;
   input		pc_in_wr_en;
   input		taken;
   input	[11:2]	int_halt_pc;
   input		halting;
   input		pc_wr_en;

   output	[11:2]	pc;

   wire		[11:2]	pc_mux_1a;
   wire		[11:2]	pc_mux_1b;
   wire			taken_or_pc_wr;
   wire		[11:2]	pc_mux_2a;
   wire		[11:2]	pc_mux_2b;
   wire		[11:2]	pc_mux_out;
   wire		[11:2]	unbuf_pc;
   wire		[11:2]	unbuf_pc_n;

   or02d1 is_or_taken_or_pc (.a1(taken), .a2(pc_in_wr_en), .z(taken_or_pc_wr));

   mx2h_10 is_pc_mux_1a (.i0({if_next_pc, 1'b0}), .i1(old_br_addr), .s(old_taken), .z(pc_mux_1a));
   mx2h_10 is_pc_mux_1b (.i0(br_addr), .i1(pc_data_in), .s(pc_in_wr_en), .z(pc_mux_1b));
   mx2h_10 is_pc_mux_2a (.i0(pc_mux_1a), .i1(pc_mux_1b), .s(taken_or_pc_wr), .z(pc_mux_2a));
   mx2h_10 is_pc_mux_2b (.i0(int_halt_pc), .i1(pc_data_in), .s(pc_in_wr_en), .z(pc_mux_2b));
   mx2h_10 is_pc_mux_3 (.i0(pc_mux_2a), .i1(pc_mux_2b), .s(halting), .z(pc_mux_out));

   spasdffen_10_0_h pc_ff (unbuf_pc, unbuf_pc_n, pc_mux_out, pc_wr_en, clk, reset_l);

   in01d5 is_pc_driver_2 (.i(unbuf_pc_n[2]), .zn(pc[2]));
   in01d5 is_pc_driver_3 (.i(unbuf_pc_n[3]), .zn(pc[3]));
   in01d5 is_pc_driver_4 (.i(unbuf_pc_n[4]), .zn(pc[4]));
   in01d5 is_pc_driver_5 (.i(unbuf_pc_n[5]), .zn(pc[5]));
   in01d5 is_pc_driver_6 (.i(unbuf_pc_n[6]), .zn(pc[6]));
   in01d5 is_pc_driver_7 (.i(unbuf_pc_n[7]), .zn(pc[7]));
   in01d5 is_pc_driver_8 (.i(unbuf_pc_n[8]), .zn(pc[8]));
   in01d5 is_pc_driver_9 (.i(unbuf_pc_n[9]), .zn(pc[9]));
   in01d5 is_pc_driver_10 (.i(unbuf_pc_n[10]), .zn(pc[10]));
   in01d5 is_pc_driver_11 (.i(unbuf_pc_n[11]), .zn(pc[11]));
endmodule


module kill_unit (sav_inst, fst_inst, sec_inst, 
	sav_su, sav_vu, fst_su_no_sav, fst_vu_no_sav, 
	single_step, kill_su_issue_pre, kill_vu_issue_pre,
	kill_su_issue, kill_vu_issue);

   input	[31:0]	sav_inst;
   input	[31:0]	fst_inst;
   input	[31:0]	sec_inst;
   input		sav_su;
   input		sav_vu;
   input		fst_su_no_sav;
   input		fst_vu_no_sav;
   input		single_step;
   input		kill_su_issue_pre;
   input		kill_vu_issue_pre;

   output		kill_su_issue;
   output		kill_vu_issue;

   hazard_unit s_f_haz (sav_inst, fst_inst, single_step, sav_su_first_hazard, sav_vu_first_hazard);
   hazard_unit f_s_haz (fst_inst, sec_inst, single_step, fst_su_first_hazard, fst_vu_first_hazard);

/*
   assign kill_su_issue = kill_su_issue_pre || 
	(sav_vu && sav_vu_first_hazard) || (fst_vu_no_sav && fst_vu_first_hazard);
   assign kill_vu_issue = kill_vu_issue_pre || 
	(sav_su && sav_su_first_hazard) || (fst_su_no_sav && fst_su_first_hazard);
*/
   ao03d2 ao_kill_su (.a1(fst_vu_no_sav), .a2(fst_vu_first_hazard), .b1(sav_vu), .b2(sav_vu_first_hazard), 
	.c(kill_su_issue_pre), .zn(kill_su_issue_l));
   ao03d2 ao_kill_vu (.a1(sav_su), .a2(sav_su_first_hazard), .b1(fst_su_no_sav), .b2(fst_su_first_hazard), 
	.c(kill_vu_issue_pre), .zn(kill_vu_issue_l));
   in01d5 in_kill_su (.i(kill_su_issue_l), .zn(kill_su_issue));
   in01d5 in_kill_vu (.i(kill_vu_issue_l), .zn(kill_vu_issue));
endmodule

module hazard_unit (first_inst, second_inst, single_step, su_first_hazard, vu_first_hazard);

   input	[31:0]	first_inst;
   input	[31:0]	second_inst;
   input		single_step;

   output		su_first_hazard;
   output		vu_first_hazard;

   wire		[4:0]	first_vs;
   wire		[4:0]	first_vt;
   wire		[4:0]	first_vd;
   wire		[4:0]	first_rt;

   wire		[4:0]	first_rd;

   wire		[4:0]	second_vs;
   wire		[4:0]	second_vt;
   wire		[4:0]	second_vd;
   wire		[4:0]	second_rt;
   wire		[4:0]	second_rd;

   wire			rt_eq_vs;
   wire			rt_eq_vt;
   wire			rt_eq_vd;

   wire			vd_eq_rt;
   wire			vd_eq_rd;

   wire			vd_eq_rt_hi;

   wire		[31:0]	f_h;		// local copy of first instruction
   wire		[31:0]	f_l;		// and its inverse
   wire		[31:0]	s_h;		// local copy of second instruction
   wire		[31:0]	s_l;		// and its inverse

   assign first_vs = f_h[15:11];
   assign first_vt = f_h[20:16];
   assign first_vd = f_h[10:6];
   assign first_rt = f_h[20:16];
   assign first_rd = f_h[15:11];

   assign second_vs = s_h[15:11];
   assign second_vt = s_h[20:16];
   assign second_vd = s_h[10:6];
   assign second_rt = s_h[20:16];
   assign second_rd = s_h[15:11];

   xor_5 xor_rt_eq_vs_5 (.a1(first_rt), .a2(second_vs), .eq(rt_eq_vs));
   xor_5 xor_rt_eq_vt_5 (.a1(first_rt), .a2(second_vt), .eq(rt_eq_vt));
   xor_5 xor_rt_eq_vd_5 (.a1(first_rt), .a2(second_vd), .eq(rt_eq_vd));

   xor_5 xor_rd_eq_vs_5 (.a1(first_rd), .a2(second_vs), .eq(rd_eq_vs));
   xor_5 xor_rd_eq_vt_5 (.a1(first_rd), .a2(second_vt), .eq(rd_eq_vt));
   xor_5 xor_rd_eq_vd_5 (.a1(first_rd), .a2(second_vd), .eq(rd_eq_vd));

   xor_5 xor_vd_eq_rt_5 (.a1(first_vd), .a2(second_rt), .eq(vd_eq_rt));
   xor_5 xor_vd_eq_rd_5 (.a1(first_vd), .a2(second_rd), .eq(vd_eq_rd));

   xor_2 xor_rt_eq_vs_2 (.a1(first_rt[4:3]), .a2(second_vs[4:3]), .eq(rt_eq_vs_hi));
   xor_2 xor_rt_eq_vt_2 (.a1(first_rt[4:3]), .a2(second_vt[4:3]), .eq(rt_eq_vt_hi));
   xor_2 xor_rt_eq_vd_2 (.a1(first_rt[4:3]), .a2(second_vd[4:3]), .eq(rt_eq_vd_hi));

   xor_2 xor_vd_eq_rt_2 (.a1(first_vd[4:3]), .a2(second_rt[4:3]), .eq(vd_eq_rt_hi));

   wire			first_lwc2;
   wire			first_mtc2_a;
   wire			first_mtc2_b;
   wire			first_mtc2;
   wire			first_lst;
   wire			first_ctc2_vc_a;
   wire			first_ctc2_vc_b;
   wire			first_ctc2_vc0_c;
   wire			first_ctc2_vc0;
   wire			first_ctc2_vc1_c;
   wire			first_ctc2_vc1;
   wire			first_ctc2_vc2_c;
   wire			first_ctc2_vc2;

   wire			second_break;
   wire			second_break_a;
   wire			second_break_b;
   wire			second_break_c;
   wire			second_nop;
   wire			second_macq;
   wire			second_sum_sar;
   wire			second_rnd;
   wire			second_sum_sar_ext;

   // In some cases instructions that don't actually have the described
   // behavior are included in the following use/set assignments for 
   // hardware convenience. 
   // vco: use_vc0: vabs and vmrg; set_vc0: vabs, vaddb, vsubb, and vmrg
   // vcc: use_vc1: vmrg, cl, cr; set_vc1: all selects 
   // 		(vmrg doesn't really set vc1, but we say it does to prevent
   // 		it from dual issuing with ctc2)
   // vce: use_vc2: cl; set_vc2: cl, ch, cr			

   wire			second_use_vs;
   wire			second_use_vt;
   wire			second_vu_rd_wr_en;
   wire			second_vu_comp;

   ni01d5_32 ni_f_buf (.i(first_inst), .z(f_h));	// All 32 bits are probably unnecessary
   in01d5_32 in_f_buf (.i(first_inst), .zn(f_l));

   ni01d5_32 ni_s_buf (.i(second_inst), .z(s_h));
   in01d5_32 in_s_buf (.i(second_inst), .zn(s_l));

// fst_inst[31:26]==6'b110010
an06d2 an_first_lwc2 	(.a1(f_h[31]), .a2(f_h[30]), .a3(f_l[29]), .a4(f_l[28]), .a5(f_h[27]), .a6(f_l[26]), .z(first_lwc2)); 

// (fst_inst[31:22]==10'b0100100010);
an04d2 an_first_mtc2_a	(.a1(f_l[31]), .a2(f_h[30]), .a3(f_l[29]), .a4(f_l[28]), .z(first_mtc2_a));	
an04d2 an_first_mtc2_b	(.a1(f_h[27]), .a2(f_l[26]), .a3(f_l[25]), .a4(f_l[24]), .z(first_mtc2_b));	
an04d2 an_first_mtc2	(.a1(f_h[23]), .a2(f_l[22]), .a3(first_mtc2_a), .a4(first_mtc2_b), .z(first_mtc2));	

// (fst_inst[14:11]==4'b1011);
an04d2 an_first_lst 	(.a1(f_h[14]), .a2(f_l[13]), .a3(f_h[12]), .a4(f_h[11]), .z(first_lst)); 

// (fst_inst[31:22]==10'b0100100011) && (fst_rd[1:0]==2'b00);
an04d2 an_first_ctc2_a	(.a1(f_l[31]), .a2(f_h[30]), .a3(f_l[29]), .a4(f_l[28]), .z(first_ctc2_vc_a));	
an04d2 an_first_ctc2_b	(.a1(f_h[27]), .a2(f_l[26]), .a3(f_l[25]), .a4(f_l[24]), .z(first_ctc2_vc_b));	
an04d2 an_first_ctc2_0c	(.a1(f_h[23]), .a2(f_h[22]), .a3(f_l[12]), .a4(f_l[11]), .z(first_ctc2_vc0_c));
an03d2 an_first_ctc2_0	(.a1(first_ctc2_vc_a), .a2(first_ctc2_vc_b), .a3(first_ctc2_vc0_c), .z(first_ctc2_vc0));  

// (fst_inst[31:22]==10'b0100100011) && (fst_rd[1:0]==2'b01); 
an04d2 an_first_ctc2_1c	(.a1(f_h[23]), .a2(f_h[22]), .a3(f_l[12]), .a4(f_h[11]), .z(first_ctc2_vc1_c));
an03d2 an_first_ctc2_1	(.a1(first_ctc2_vc_a), .a2(first_ctc2_vc_b), .a3(first_ctc2_vc1_c), .z(first_ctc2_vc1));  

// (fst_inst[31:22]==10'b0100100011) && (fst_rd[1:0]==2'b10);
an04d2 an_first_ctc2_2c	(.a1(f_h[23]), .a2(f_h[22]), .a3(f_h[12]), .a4(f_l[11]), .z(first_ctc2_vc2_c));
an03d2 an_first_ctc2_2	(.a1(first_ctc2_vc_a), .a2(first_ctc2_vc_b), .a3(first_ctc2_vc2_c), .z(first_ctc2_vc2));  

// second_break
an04d2 an_second_break_a (.a1(f_l[31]), .a2(f_l[30]), .a3(f_l[29]), .a4(f_l[28]), .z(second_break_a));
an04d2 an_second_break_b (.a1(f_l[27]), .a2(f_l[26]), .a3(f_l[5]), .a4(f_l[4]), .z(second_break_b));
an04d2 an_second_break_c (.a1(f_h[3]), .a2(f_h[2]), .a3(f_l[1]), .a4(f_h[0]), .z(second_break_c));
an03d2 an_second_break	(.a1(second_break_a), .a2(second_break_b), .a3(second_break_c), .z(second_break));

// (second_cfc2 || second_ctc2) && fst_rd[1:0] == vcx
// = (second_inst[31:24]==8'b01001000 && second_inst[22]==1'b1); 
an04d2 an_second_ctcf_a	(.a1(s_l[31]), .a2(s_h[30]), .a3(s_l[29]), .a4(s_l[28]), .z(second_ctcf_vc_a));	
an05d2 an_second_ctcf_b	(.a1(s_h[27]), .a2(s_l[26]), .a3(s_l[25]), .a4(s_l[24]), .a5(s_h[22]), .z(second_ctcf_vc_b));	
an04d2 an_second_ctcf0	(.a1(s_l[12]), .a2(s_l[11]), .a3(second_ctcf_vc_a), .a4(second_ctcf_vc_b), .z(second_ctcf_vc0));	
an04d2 an_second_ctcf1	(.a1(s_l[12]), .a2(s_h[11]), .a3(second_ctcf_vc_a), .a4(second_ctcf_vc_b), .z(second_ctcf_vc1));	
an04d2 an_second_ctcf2	(.a1(s_h[12]), .a2(s_l[11]), .a3(second_ctcf_vc_a), .a4(second_ctcf_vc_b), .z(second_ctcf_vc2));	

// (second_inst[5:0] == 6'b11x111)
an05d2 an_second_nop	(.a1(s_h[5]), .a2(s_h[4]), .a3(s_h[2]), .a4(s_h[1]), .a5(s_h[0]), .z(second_nop));
nd05d2 an_second_nop_l	(.a1(s_h[5]), .a2(s_h[4]), .a3(s_h[2]), .a4(s_h[1]), .a5(s_h[0]), .zn(second_nop_l));
// (second_inst[5:0] == 6'b001011)
an06d2 an_second_macq	(.a1(s_l[5]), .a2(s_l[4]), .a3(s_h[3]), .a4(s_l[2]), .a5(s_h[1]), .a6(s_h[0]), .z(second_macq));
// (second_inst[5:2] == 6'b0111)
an04d2 an_second_smsr	(.a1(s_l[5]), .a2(s_h[4]), .a3(s_h[3]), .a4(s_h[2]), .z(second_sum_sar));
// (second_inst[5:0] == 6'b00x010)
an05d2 an_second_rnd	(.a1(s_l[5]), .a2(s_l[4]), .a3(s_l[2]), .a4(s_h[1]), .a5(s_l[0]), .z(second_rnd));
// (second_inst[5:2] == 6'bx111)
an03d2 an_second_smsrex	(.a1(s_h[4]), .a2(s_h[3]), .a3(s_h[2]), .z(second_sum_sar_ext));

// (second_inst[31:25] == 7'b0100101);
an04d2 an_second_comp_a	(.a1(s_l[31]), .a2(s_h[30]), .a3(s_l[29]), .a4(s_l[28]), .z(second_vu_comp_a));
an04d2 an_second_comp	(.a1(s_h[27]), .a2(s_l[26]), .a3(s_h[25]), .a4(second_vu_comp_a), .z(second_vu_comp));

// sec_vu_comp && (second_inst[5:3] == 3'b010) 
an04d2 an_second_us0_a	(.a1(second_vu_comp), .a2(s_l[5]), .a3(s_h[4]), .a4(s_l[3]), .z(second_vu_us0_a));
// sec_vu_comp && (second_inst[5:3] == 3'b100) 
an04d2 an_second_us1	(.a1(second_vu_comp), .a2(s_h[5]), .a3(s_l[4]), .a4(s_l[3]), .z(second_vu_us1));
or02d1 or_second_us0	(.a1(second_vu_us0_a), .a2(second_vu_us1), .z(second_vu_us0));

// ((second_inst[5:1]==5'b10010x) || (second_inst[5:0]==6'b100110)
an05d2 an_second_us2a	(.a1(second_vu_comp), .a2(s_h[5]), .a3(s_l[4]), .a4(s_l[3]), .a5(s_h[2]), .z(second_vu_us2a));
or02d1 oa_second_us2b 	(.a1(s_l[1]), .a2(s_l[0]), .z(second_vu_us2b));
an02d1 an_second_us2	(.a1(second_vu_us2a), .a2(second_vu_us2b), .z(second_vu_us2));
/*
second_set_vc0	= second_use_or_set_vc0;
second_set_vc1	= second_use_or_set_vc1;
second_set_vc2	= second_use_or_set_vc2;
*/
// sec_vu_comp && !(second_nop || second_macq || second_sum_sar || second_rnd) 
nr04d1 nr_use_vs 	(.a1(second_nop), .a2(second_macq), .a3(second_sum_sar), .a4(second_rnd), .zn(second_use_vs_a));
an02d1 an_use_vs	(.a1(second_vu_comp), .a2(second_use_vs_a), .z(second_use_vs));

// sec_vu_comp && !(second_nop || second_macq || second_sum_sar_ext);
nr03d1 nr_use_vt 	(.a1(second_nop), .a2(second_macq), .a3(second_sum_sar_ext), .zn(second_use_vt_a));
an02d1 an_use_vt	(.a1(second_vu_comp), .a2(second_use_vt_a), .z(second_use_vt));

an02d3 an_second_rdwren	(.a1(second_vu_comp), .a2(second_nop_l), .z(second_vu_rd_wr_en));

an03d2 an_haz_term_su_0		(.a1(first_lwc2), .a2(rt_eq_vs), .a3(second_use_vs), .z(term_su0));
an03d2 an_haz_term_su_1		(.a1(first_lwc2), .a2(rt_eq_vt), .a3(second_use_vt), .z(term_su1));
an03d2 an_haz_term_su_2		(.a1(first_lwc2), .a2(rt_eq_vd), .a3(second_vu_rd_wr_en), .z(term_su2));
an03d2 an_haz_term_su_3		(.a1(first_mtc2), .a2(rd_eq_vs), .a3(second_use_vs), .z(term_su3));
an03d2 an_haz_term_su_4		(.a1(first_mtc2), .a2(rd_eq_vt), .a3(second_use_vt), .z(term_su4));
an03d2 an_haz_term_su_5		(.a1(first_mtc2), .a2(rd_eq_vd), .a3(second_vu_comp), .z(term_su5));
an04d2 an_haz_term_su_6		(.a1(first_lwc2), .a2(first_lst), .a3(rt_eq_vs_hi), .a4(second_use_vs), .z(term_su6));
an04d2 an_haz_term_su_7		(.a1(first_lwc2), .a2(first_lst), .a3(rt_eq_vt_hi), .a4(second_use_vt), .z(term_su7));
an04d2 an_haz_term_su_8		(.a1(first_lwc2), .a2(first_lst), .a3(rt_eq_vd_hi), .a4(second_vu_comp), .z(term_su8));
an02d2 an_haz_term_su_9		(.a1(first_ctc2_vc0), .a2(second_vu_us0), .z(term_su9));
an02d2 an_haz_term_su_10	(.a1(first_ctc2_vc1), .a2(second_vu_us1), .z(term_su10));
an02d2 an_haz_term_su_11	(.a1(first_ctc2_vc2), .a2(second_vu_us2), .z(term_su11));

or04d2 or_haz_term_su_a	(.a1(term_su0), .a2(term_su1), .a3(term_su2), .a4(term_su3), .z(term_su_a));
or04d2 or_haz_term_su_b	(.a1(term_su4), .a2(term_su5), .a3(term_su6), .a4(term_su7), .z(term_su_b));
or04d2 or_haz_term_su_c	(.a1(term_su8), .a2(term_su9), .a3(term_su10), .a4(term_su11), .z(term_su_c));
or04d2 or_haz_term_su	(.a1(term_su_a), .a2(term_su_b), .a3(term_su_c), .a4(single_step), .z(su_first_hazard));


// (first_inst[5:0] == 6'b11x111)
nd05d2 an_first_nop_l	(.a1(f_h[5]), .a2(f_h[4]), .a3(f_h[2]), .a4(f_h[1]), .a5(f_h[0]), .zn(first_nop_l));
// (first_inst[31:25] == 7'b0100101);
an04d2 an_first_comp_a	(.a1(f_l[31]), .a2(f_h[30]), .a3(f_l[29]), .a4(f_l[28]), .z(first_vu_comp_a));
an04d2 an_first_comp	(.a1(f_h[27]), .a2(f_l[26]), .a3(f_h[25]), .a4(first_vu_comp_a), .z(first_vu_comp));

an02d3 an_first_rdwren	(.a1(first_vu_comp), .a2(first_nop_l), .z(first_vu_rd_wr_en));

// second_lwc2: second_inst[31:26]==6'b110010
an06d2 an_second_lwc2 	(.a1(s_h[31]), .a2(s_h[30]), .a3(s_l[29]), .a4(s_l[28]), .a5(s_h[27]), .a6(s_l[26]), .z(second_lwc2)); 
// second_swc2: second_inst[31:26]==6'b111010
an06d2 an_second_swc2 	(.a1(s_h[31]), .a2(s_h[30]), .a3(s_h[29]), .a4(s_l[28]), .a5(s_h[27]), .a6(s_l[26]), .z(second_swc2)); 
// load/store transpose: second_lst: second_inst[14:11]==4'b1011
an04d2 an_second_lst 	(.a1(s_h[14]), .a2(s_l[13]), .a3(s_h[12]), .a4(s_h[11]), .z(second_lst)); 

// first_vu_comp && (first_inst[5:3] == 3'b010) 
an04d2 an_first_us0_a	(.a1(first_vu_comp), .a2(f_l[5]), .a3(f_h[4]), .a4(f_l[3]), .z(first_vu_us0_a));
// first_vu_comp && (first_inst[5:3] == 3'b100) 
an04d2 an_first_us1	(.a1(first_vu_comp), .a2(f_h[5]), .a3(f_l[4]), .a4(f_l[3]), .z(first_vu_us1));
or02d1 or_first_us0	(.a1(first_vu_us0_a), .a2(first_vu_us1), .z(first_vu_us0));

// ((first_inst[5:1]==5'b10010x) || (first_inst[5:0]==6'b100110)
an05d2 an_first_us2a	(.a1(first_vu_comp), .a2(f_h[5]), .a3(f_l[4]), .a4(f_l[3]), .a5(f_h[2]), .z(first_vu_us2a));
or02d1 oa_first_us2b 	(.a1(f_l[1]), .a2(f_l[0]), .z(first_vu_us2b));
an02d1 an_first_us2	(.a1(first_vu_us2a), .a2(first_vu_us2b), .z(first_vu_us2));
/*
first_set_vc0	= first_use_or_set_vc0;
first_set_vc1	= first_use_or_set_vc1;
first_set_vc2	= first_use_or_set_vc2;
*/
// (sec_inst[31:22]==10'b0100100010);
an04d2 an_second_mtc2_a	(.a1(s_l[31]), .a2(s_h[30]), .a3(s_l[29]), .a4(s_l[28]), .z(second_mtc2_a));	
an04d2 an_second_mtc2_b	(.a1(s_h[27]), .a2(s_l[26]), .a3(s_l[25]), .a4(s_l[24]), .z(second_mtc2_b));	
an04d2 an_second_mtc2	(.a1(s_h[23]), .a2(s_l[22]), .a3(second_mtc2_a), .a4(second_mtc2_b), .z(second_mtc2));	
// (sec_inst[31:22]==10'b0100100000);
an04d2 an_second_mfc2_a	(.a1(s_l[31]), .a2(s_h[30]), .a3(s_l[29]), .a4(s_l[28]), .z(second_mfc2_a));	
an04d2 an_second_mfc2_b	(.a1(s_h[27]), .a2(s_l[26]), .a3(s_l[25]), .a4(s_l[24]), .z(second_mfc2_b));	
an04d2 an_second_mfc2	(.a1(s_l[23]), .a2(s_l[22]), .a3(second_mfc2_a), .a4(second_mfc2_b), .z(second_mfc2));	

ni01d2 ni_haz_term_vu_0		(.i(second_break), .z(term_vu0));
an03d2 an_haz_term_vu_1		(.a1(first_vu_rd_wr_en), .a2(vd_eq_rt), .a3(second_swc2), .z(term_vu1));
an03d2 an_haz_term_vu_2		(.a1(first_vu_rd_wr_en), .a2(vd_eq_rd), .a3(second_mfc2), .z(term_vu2));
an03d2 an_haz_term_vu_3		(.a1(first_vu_rd_wr_en), .a2(vd_eq_rd), .a3(second_mtc2), .z(term_vu3));
an03d2 an_haz_term_vu_4		(.a1(first_vu_rd_wr_en), .a2(vd_eq_rt), .a3(second_lwc2), .z(term_vu4));
an04d2 an_haz_term_vu_5		(.a1(first_vu_rd_wr_en), .a2(vd_eq_rt_hi), .a3(second_swc2), .a4(second_lst), .z(term_vu5));
an04d2 an_haz_term_vu_6		(.a1(first_vu_rd_wr_en), .a2(vd_eq_rt_hi), .a3(second_lwc2), .a4(second_lst), .z(term_vu6));
an02d2 an_haz_term_vu_7		(.a1(first_vu_us0), .a2(second_ctcf_vc0), .z(term_vu7));
an02d2 an_haz_term_vu_8		(.a1(first_vu_us1), .a2(second_ctcf_vc1), .z(term_vu8));
an02d2 an_haz_term_vu_9		(.a1(first_vu_us2), .a2(second_ctcf_vc2), .z(term_vu9));

or04d2 or_haz_term_vu_a	(.a1(term_vu0), .a2(term_vu1), .a3(term_vu2), .a4(term_vu3), .z(term_vu_a));
or04d2 or_haz_term_vu_b	(.a1(term_vu4), .a2(term_vu5), .a3(term_vu6), .a4(term_vu7), .z(term_vu_b));
or02d2 or_haz_term_vu_c	(.a1(term_vu8), .a2(term_vu9), .z(term_vu_c));
or04d2 or_haz_term_vu	(.a1(term_vu_a), .a2(term_vu_b), .a3(term_vu_c), .a4(single_step), .z(vu_first_hazard));

endmodule

module xor_5 (a1, a2, eq);

   input	[4:0]	a1;
   input	[4:0]	a2;

   output		eq;

   wire		[4:0]	z;

   xo02d1 xor_bit_0 (.a1(a1[0]), .a2(a2[0]), .z(z[0]));
   xo02d1 xor_bit_1 (.a1(a1[1]), .a2(a2[1]), .z(z[1]));
   xo02d1 xor_bit_2 (.a1(a1[2]), .a2(a2[2]), .z(z[2]));
   xo02d1 xor_bit_3 (.a1(a1[3]), .a2(a2[3]), .z(z[3]));
   xo02d1 xor_bit_4 (.a1(a1[4]), .a2(a2[4]), .z(z[4]));

   nr05d1 xnr_5 (.a1(z[0]), .a2(z[1]), .a3(z[2]), .a4(z[3]), .a5(z[4]), .zn(eq));

endmodule

module xor_2 (a1, a2, eq);

   input	[1:0]	a1;
   input	[1:0]	a2;

   output		eq;

   wire		[1:0]	z;

   xo02d1 xor_bit_0 (.a1(a1[0]), .a2(a2[0]), .z(z[0]));
   xo02d1 xor_bit_1 (.a1(a1[1]), .a2(a2[1]), .z(z[1]));

   nr02d1 xor_2 (.a1(z[0]), .a2(z[1]), .zn(eq));

endmodule

module in01d5_32(i, zn);

   input	[31:0]	i;
   output	[31:0]	zn;

in01d5 u_00(.zn(zn[ 0]), .i(i[ 0]));
in01d5 u_01(.zn(zn[ 1]), .i(i[ 1]));
in01d5 u_02(.zn(zn[ 2]), .i(i[ 2]));
in01d5 u_03(.zn(zn[ 3]), .i(i[ 3]));
in01d5 u_04(.zn(zn[ 4]), .i(i[ 4]));
in01d5 u_05(.zn(zn[ 5]), .i(i[ 5]));
in01d5 u_06(.zn(zn[ 6]), .i(i[ 6]));
in01d5 u_07(.zn(zn[ 7]), .i(i[ 7]));

in01d5 u_08(.zn(zn[ 8]), .i(i[ 8]));
in01d5 u_09(.zn(zn[ 9]), .i(i[ 9]));
in01d5 u_10(.zn(zn[10]), .i(i[10]));
in01d5 u_11(.zn(zn[11]), .i(i[11]));
in01d5 u_12(.zn(zn[12]), .i(i[12]));
in01d5 u_13(.zn(zn[13]), .i(i[13]));
in01d5 u_14(.zn(zn[14]), .i(i[14]));
in01d5 u_15(.zn(zn[15]), .i(i[15]));

in01d5 u_16(.zn(zn[16]), .i(i[16]));
in01d5 u_17(.zn(zn[17]), .i(i[17]));
in01d5 u_18(.zn(zn[18]), .i(i[18]));
in01d5 u_19(.zn(zn[19]), .i(i[19]));
in01d5 u_20(.zn(zn[20]), .i(i[20]));
in01d5 u_21(.zn(zn[21]), .i(i[21]));
in01d5 u_22(.zn(zn[22]), .i(i[22]));
in01d5 u_23(.zn(zn[23]), .i(i[23]));

in01d5 u_24(.zn(zn[24]), .i(i[24]));
in01d5 u_25(.zn(zn[25]), .i(i[25]));
in01d5 u_26(.zn(zn[26]), .i(i[26]));
in01d5 u_27(.zn(zn[27]), .i(i[27]));
in01d5 u_28(.zn(zn[28]), .i(i[28]));
in01d5 u_29(.zn(zn[29]), .i(i[29]));
in01d5 u_30(.zn(zn[30]), .i(i[30]));
in01d5 u_31(.zn(zn[31]), .i(i[31]));
   
endmodule

module ni01d5_32(i, z);

   input	[31:0]	i;
   output	[31:0]	z;

ni01d5 u_00(.z(z[ 0]), .i(i[ 0]));
ni01d5 u_01(.z(z[ 1]), .i(i[ 1]));
ni01d5 u_02(.z(z[ 2]), .i(i[ 2]));
ni01d5 u_03(.z(z[ 3]), .i(i[ 3]));
ni01d5 u_04(.z(z[ 4]), .i(i[ 4]));
ni01d5 u_05(.z(z[ 5]), .i(i[ 5]));
ni01d5 u_06(.z(z[ 6]), .i(i[ 6]));
ni01d5 u_07(.z(z[ 7]), .i(i[ 7]));

ni01d5 u_08(.z(z[ 8]), .i(i[ 8]));
ni01d5 u_09(.z(z[ 9]), .i(i[ 9]));
ni01d5 u_10(.z(z[10]), .i(i[10]));
ni01d5 u_11(.z(z[11]), .i(i[11]));
ni01d5 u_12(.z(z[12]), .i(i[12]));
ni01d5 u_13(.z(z[13]), .i(i[13]));
ni01d5 u_14(.z(z[14]), .i(i[14]));
ni01d5 u_15(.z(z[15]), .i(i[15]));

ni01d5 u_16(.z(z[16]), .i(i[16]));
ni01d5 u_17(.z(z[17]), .i(i[17]));
ni01d5 u_18(.z(z[18]), .i(i[18]));
ni01d5 u_19(.z(z[19]), .i(i[19]));
ni01d5 u_20(.z(z[20]), .i(i[20]));
ni01d5 u_21(.z(z[21]), .i(i[21]));
ni01d5 u_22(.z(z[22]), .i(i[22]));
ni01d5 u_23(.z(z[23]), .i(i[23]));

ni01d5 u_24(.z(z[24]), .i(i[24]));
ni01d5 u_25(.z(z[25]), .i(i[25]));
ni01d5 u_26(.z(z[26]), .i(i[26]));
ni01d5 u_27(.z(z[27]), .i(i[27]));
ni01d5 u_28(.z(z[28]), .i(i[28]));
ni01d5 u_29(.z(z[29]), .i(i[29]));
ni01d5 u_30(.z(z[30]), .i(i[30]));
ni01d5 u_31(.z(z[31]), .i(i[31]));
   
endmodule

module muxed_inst (clk, reset_l, should_have_stalled, stalled_rd_inst, rd_inst, muxed_rd_inst);

   input			clk;
   input			reset_l;
   input			should_have_stalled;
   input		[63:0]	stalled_rd_inst;
   input		[63:0]	rd_inst;

   output		[63:0]	muxed_rd_inst;

   wire				prev_stalled_a;
   wire				prev_stalled_a_n;
   wire				prev_stalled_b;
   wire				prev_stalled_b_n;

   dfctnh mx_inst_prev_st_a (.q(prev_stalled_a), .qn(prev_stalled_a_n), .d(should_have_stalled), .cp(clk), .cdn(reset_l)); 
   dfctnh mx_inst_prev_st_b (.q(prev_stalled_b), .qn(prev_stalled_b_n), .d(should_have_stalled), .cp(clk), .cdn(reset_l)); 
   mx2h_32 mx_32_muxed_inst_hi (.i0(rd_inst[63:32]), .i1(stalled_rd_inst[63:32]), .s(prev_stalled_a), .z(muxed_rd_inst[63:32]));
   mx2h_32 mx_32_muxed_inst_lo (.i0(rd_inst[31:0]), .i1(stalled_rd_inst[31:0]), .s(prev_stalled_b), .z(muxed_rd_inst[31:0]));

endmodule

/* 
History/Documentation for kill_unit
   assign kill_su_issue = rd_other_bubble_tmp || (rd_bubble && !delay_slot) || 
     	((su_inst_sel[1]||su_inst_sel[3])&&s_f_dep) || 
	((vu_inst_sel[1] || vu_inst_sel[3]) && f_s_dep) ||
	no_su_inst;

   assign kill_vu_issue = rd_other_bubble_tmp || (rd_bubble && !delay_slot) || 
	((vu_inst_sel[1] || vu_inst_sel[3]) && s_f_dep) ||
	((su_inst_sel[1] || su_inst_sel[3]) && f_s_dep) ||
	no_vu_inst;

   assign s_f_dep = sav_fst_hazard || ((sav_su || sav_vu) && single_step);
   assign f_s_dep = fst_sec_hazard || ((!sav_su && !sav_vu) && single_step);

   assign sav_fst_hazard = 
    (sav_su && (
    	(sav_lwc2 && (sav_rt == fst_vs) && fst_use_vs) ||
        (sav_lwc2 && (sav_rt == fst_vt) && fst_use_vt) ||
        (sav_lwc2 && (sav_rt == fst_vd) && fst_vu_rd_wr_en) ||  // dest to dest
        (sav_mtc2 && (sav_rd==fst_vs) && fst_use_vs) ||
        (sav_mtc2 && (sav_rd==fst_vt) && fst_use_vt) ||
        (sav_mtc2 && (sav_rd==fst_vd) && fst_vu_comp) ||    // dest to dest
        (sav_lwc2 &&sav_lst&&(sav_rt[4:3]==fst_vs[4:3])&&fst_use_vs) ||
        (sav_lwc2 &&sav_lst&&(sav_rt[4:3]==fst_vt[4:3])&&fst_use_vt) ||
        (sav_lwc2 &&sav_lst&&(sav_rt[4:3]==fst_vd[4:3])&&fst_vu_comp) || // dest to dest
        (sav_ctc2_vc0 && (fst_use_vc0 || fst_set_vc0)) ||
        (sav_ctc2_vc1 && (fst_use_vc1 || fst_set_vc1)) ||
        (sav_ctc2_vc2 && (fst_use_vc2 || fst_set_vc2)))) ||
   (sav_vu && (
	(fst_break) || 						// always single-issue break 
        (sav_vu_rd_wr_en && (sav_vd == fst_rt) && fst_swc2) || 
        (sav_vu_rd_wr_en && (sav_vd == fst_rd) && fst_mfc2) || 
        (sav_vu_rd_wr_en && (sav_vd == fst_rd) && fst_mtc2) ||  // dest to dest
        (sav_vu_rd_wr_en && (sav_vd == fst_rt) && fst_lwc2) ||  // dest to dest
        (sav_vu_rd_wr_en && (sav_vd[4:3]==fst_rt[4:3]) && fst_swc2&&fst_lst) ||
        (sav_vu_rd_wr_en && (sav_vd[4:3]==fst_rt[4:3]) && fst_lwc2 && fst_lst) || // dest to dest
        (sav_set_vc0 && (fst_cfc2_vc0 || fst_ctc2_vc0)) ||
        (sav_set_vc1 && (fst_cfc2_vc1 || fst_ctc2_vc1)) || 
        (sav_set_vc2 && (fst_cfc2_vc2 || fst_ctc2_vc2))));

   assign fst_sec_hazard = !odd_target && !sav_su && !sav_vu && 
    ((!fst_vu && (
        (fst_lwc2 && (fst_rt == sec_vs) && sec_use_vs) ||
        (fst_lwc2 && (fst_rt == sec_vt) && sec_use_vt) ||
        (fst_lwc2 && (fst_rt == sec_vd) && sec_vu_rd_wr_en) ||  // dest to dest
        (fst_mtc2 && (fst_rd==sec_vs) && sec_use_vs) ||
        (fst_mtc2 && (fst_rd==sec_vt) && sec_use_vt) ||
        (fst_mtc2 && (fst_rd==sec_vd) && sec_vu_rd_wr_en) ||    // dest to dest
        (fst_lwc2 &&fst_lst&&(fst_rt[4:3]==sec_vs[4:3])&&sec_use_vs) ||
        (fst_lwc2 &&fst_lst&&(fst_rt[4:3]==sec_vt[4:3])&&sec_use_vt) ||
        (fst_lwc2 &&fst_lst&&(fst_rt[4:3]==sec_vd[4:3])&&sec_vu_comp) || // dest to dest
        (fst_ctc2_vc0 && (sec_use_vc0 || sec_set_vc0)) ||
        (fst_ctc2_vc1 && (sec_use_vc1 || sec_set_vc1)) ||
        (fst_ctc2_vc2 && (sec_use_vc2 || sec_set_vc2)))) ||
    (fst_vu && (
	(sec_break) || 						// always single-issue break
        (fst_vu_rd_wr_en && (fst_vd == sec_rt) && sec_swc2) || 
        (fst_vu_rd_wr_en && (fst_vd == sec_rd) && sec_mfc2) || 
        (fst_vu_rd_wr_en && (fst_vd == sec_rd) && sec_mtc2) ||  // dest to dest
        (fst_vu_rd_wr_en && (fst_vd == sec_rt) && sec_lwc2) ||  // dest to dest
        (fst_vu_rd_wr_en && (fst_vd[4:3]==sec_rt[4:3]) && sec_swc2&&sec_lst) ||
        (fst_vu_rd_wr_en && (fst_vd[4:3]==sec_rt[4:3]) && sec_lwc2 && sec_lst) || // dest to dest
        (fst_set_vc0 && (sec_cfc2_vc0 || sec_ctc2_vc0)) ||
        (fst_set_vc1 && (sec_cfc2_vc1 || sec_ctc2_vc1)) || 
        (fst_set_vc2 && (sec_cfc2_vc2 || sec_ctc2_vc2)))));
*/