issue.ss
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = issue
wire_load = 256000
standard_load = 0.01
clock = clk
default_input_delay = 1.5
default_output_delay = 1.0
default_input_load = 20
default_output_load = 20
default_drive_cell = dfntnh
default_drive_pin = q
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = {. \
/ecad/synopsys/current/libraries/syn \
/ecad/reality/lib/synopsys/nec35_v2.1 \
/ecad/reality/lib/synopsys/rcp_lib \
../src };
read -f verilog issue.v
read -f verilog ../../rsp/src/spasdff_1_1.v
read -f verilog ../../rsp/src/spasdff_1_0.v
read -f verilog ../../rsp/src/spasdff_1_0_h.v
read -f verilog ../../rsp/src/spasdff_3_0.v
read -f verilog ../../rsp/src/spasdff_4_0.v
read -f verilog ../../rsp/src/spasdff_5_0.v
read -f verilog ../../rsp/src/spasdff_6_0.v
read -f verilog ../../rsp/src/spasdff_24_0.v
read -f verilog ../../rsp/src/spasdff_32_0.v
read -f verilog ../../rsp/src/spasdffen_1_0.v
read -f verilog ../../rsp/src/spasdffen_9_0.v
read -f verilog ../../rsp/src/spasdffen_10_0.v
read -f verilog ../../rsp/src/spasdffen_10_0_h.v
read -f verilog ../../rsp/src/spasdffen_32_0.v
read -f verilog ../../rsp/src/spasdffen_64_h.v
current_design = module
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
/* set_max_area 0 */
create_clock clk -period 16.0 -waveform {0.0 8.0}
set_input_delay default_input_delay -clock clk all_inputs()
set_output_delay default_output_delay -clock clk all_outputs()
set_load default_output_load * standard_load all_outputs()
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs()
/*****************************************************************************/
/* clock and reset constraints */
/*****************************************************************************/
set_drive 0 clock
set_arrival 0 clock
set_dont_touch_network clock
set_driving_cell -cell ni01d5 -pin z reset_l
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_max_transition 3.0 module
include module + ".con"
/*****************************************************************************/
/* check */
/*****************************************************************************/
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
ungroup -flatten *_ff
ungroup -flatten *inst_unit
ungroup -flatten *pc_mux
ungroup -flatten *kill_unit
ungroup -flatten *muxed_inst
current_design = inst_mux_new
uniquify
compile
current_design = mx2h_32
uniquify
compile
current_design = module
set_dont_touch *_ff*
set_dont_touch *inst_unit*
set_dont_touch *pc_mux*
set_dont_touch *kill_unit*
set_dont_touch *hazard_unit*
set_dont_touch *muxed_inst*
set_dont_touch *mx_clr_taken*
set_dont_touch *mx_set_taken*
set_dont_touch *mx_wr_taken*
set_dont_touch *mx_xpose_*_*
set_dont_touch *st_xpose_buf*
set_dont_touch *halt_pc_mux*
compile -no_map
set_dont_touch *_ff* false
compile -map_effort high -ungroup_all -incremental_mapping
set_clock_skew -uncertainty 1 clk
set_fix_hold all_clocks()
compile -prioritize_min_paths -only_design_rule -incremental_mapping
/*****************************************************************************/
/* write */
/*****************************************************************************/
report -reference
report_constraint -all_violators > "report." + module + ".viol"
report_timing -from all_inputs() -max_paths 50 -nets > "report." + module + ".inputs"
report_timing -to all_outputs() -max_paths 50 -nets > "report." + module + ".outputs"
report_timing -path full -to su_inst -delay max -max_paths 2
report_timing -path full -to vu_inst -delay max -max_paths 2
report_timing -path full -to kill_su_issue -delay max -max_paths 2
report_timing -path full -to kill_vu_issue -delay max -max_paths 2
write -format edif -hierarchy -o module + ".edf" module
write -format verilog -hierarchy -o module + ".vsyn" module
write -format db -hierarchy -o module + ".db" module
quit