su.ss
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = su
wire_load = 256000
standard_load = 0.01
clock = clk
default_input_delay = 1.5
default_output_delay = 1.0
default_input_load = 20
default_output_load = 70
default_drive_cell = dfntnh
default_drive_pin = q
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = {. \
/ecad/synopsys/current/libraries/syn \
/ecad/reality/lib/synopsys/nec35_v2.1 \
/ecad/reality/lib/synopsys/rcp_lib \
../src \
../../syn};
read -f verilog ../src/su.v
read -f edif suctl.edf
read -f edif sudp_sc.edf
current_design = module
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
/* set_max_area 0 */
set_dont_touch { ne35hd130d/nt01d* }
create_clock clock -period 16.0 -waveform {0.0 8.0}
set_clock_skew -uncertainty 1 clock
set_input_delay default_input_delay -clock clock all_inputs()
set_output_delay default_output_delay -clock clock all_outputs()
set_load default_output_load * standard_load all_outputs()
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs()
/*****************************************************************************/
/* clock and reset constraints */
/*****************************************************************************/
set_drive 0 clock
set_arrival 0 clock
set_dont_touch_network clock
set_driving_cell -cell ni01d5 -pin z reset_l
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_max_transition 2.0 module
include module + ".con"
set_false_path -from {ls_data[0]} -to {rd_base[0]}
set_false_path -from {ls_data[1]} -to {rd_base[1]}
set_false_path -from {ls_data[2]} -to {rd_base[2]}
set_false_path -from {ls_data[3]} -to {rd_base[3]}
/*****************************************************************************/
/* check */
/*****************************************************************************/
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
set_dont_touch suctl
set_dont_touch sudp_sc
/* compile_no_new_cells_at_top_level = "true" */
/* compile -map_effort low -ungroup_all */
link
report -reference
report_constraint -all_violators > "report." + module + ".viol"
report_timing -path full -delay max -max_paths 50 > "report." + module + ".max_paths"
report_timing -from all_inputs() -max_paths 10 -nets > "report." + module + ".input"
report_timing -to all_outputs() -max_paths 10 -nets > "report." + module + ".output"
write -format edif -hierarchy -o module + ".edf" module
write -format verilog -hierarchy -o module + ".vsyn" module
write -format db -hierarchy -o module + ".db" module
include "su.tmg"
include "report.dc"
quit