suvuctl.ss
4.86 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = suvuctl
wire_load = 256000
standard_load = 0.01
clock = clk
default_input_delay = 1.5
default_output_delay = 1.0
default_max_delay = 15.0
default_input_load = 20
default_output_load = 20
default_drive_cell = dfntnh
default_drive_pin = q
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = {. \
/ecad/synopsys/current/libraries/syn \
/ecad/reality/lib/synopsys/nec35_v2.1 \
/ecad/reality/lib/synopsys/rcp_lib \
../src };
read -f verilog ../src/suvuctl.v
read -f verilog ../../rsp/src/sp_5_32_decode.v
read -f verilog ../../rsp/src/spasdff_4_0.v
read -f verilog ../../rsp/src/spasdff_10_0.v
read -f verilog ../../rsp/src/spasdff_5_0.v
read -f verilog ../../rsp/src/spasdff_12_0.v
read -f verilog ../../rsp/src/spasdff_6_0.v
read -f verilog ../../rsp/src/spasdff_1_0.v
read -f verilog ../../rsp/src/spasdff_9_0.v
read -f verilog ../../rsp/src/spasdff_1_1.v
read -f verilog ../../rsp/src/spasdffen_10_0.v
read -f verilog ../../rsp/src/spasdff_24_0.v
read -f verilog ../../rsp/src/spasdffen_1_0.v
read -f verilog ../../rsp/src/spasdff_32_0.v
read -f verilog ../../rsp/src/spasdffen_32_0.v
read -f verilog ../../rsp/src/spasdff_3_0.v
read -f verilog ../../rsp/src/spasdffen_9_0.v
current_design = module
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
/* set_max_area 0 */
set_dont_touch { ne35hd130d/nt01d* }
create_clock clock -period 16.0 -waveform {0.0 8.0}
set_input_delay default_input_delay -clock clock all_inputs()
set_output_delay default_output_delay -clock clock all_outputs()
set_load default_output_load * standard_load all_outputs()
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs()
/*****************************************************************************/
/* clock and reset constraints */
/*****************************************************************************/
set_drive 0 clock
set_arrival 0 clock
set_dont_touch_network clock
set_driving_cell -cell ni01d5 -pin z reset_l
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_max_fanout 8 module
set_max_transition 2.0 module
include module + ".con"
/*****************************************************************************/
/* check */
/*****************************************************************************/
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
ungroup -flatten *_ff
set_dont_touch *_ff*
set_flatten -phase true -effort high -minimize single_output
set_structure false
compile -flatten_minimize single_output -flatten_effort high -flatten_phase \
-map_effort high -incremental_mapping -prioritize_min_paths
set_clock_skew -uncertainty 1 clock
set_fix_hold all_clocks()
compile -prioritize_min_paths -only_design_rule -incremental_mapping
/*
set_dont_touch *_ff* false
compile -map_effort high -ungroup_all -incremental_mapping
*/
/*****************************************************************************/
/* write */
/*****************************************************************************/
report -reference
report_constraint -all_violators > "report." + module + ".viol"
report_timing -from all_inputs() -max_paths 500 -nets > "report." + module + ".input"
report_timing -to all_outputs() -max_paths 500 -nets > "report." + module + ".output"
write -format edif -hierarchy -o module + ".edf" module
write -format verilog -hierarchy -o module + ".vsyn" module
write -format db -hierarchy -o module + ".db" module
quit