tm.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: tm.v,v 1.1.1.1 2002/05/17 06:14:58 blythe Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: tm
// description: Texture Memory Unit
//
// designer: Tony DeLaurier
// date: 7/11/94
//
////////////////////////////////////////////////////////////////////////
`timescale 10ps / 10ps //1unit = 0.01ns
module tm (gclk, reset_l, bist_go, bist_check, iddq, tlut_en, tlut_type, adrs_bnk0l,
adrs_bnk1l, adrs_bnk2l, adrs_bnk3l, adrs_bnk0h, adrs_bnk1h, adrs_bnk2h,
adrs_bnk3h, adrs_a, adrs_b_ba, adrs_c, adrs_d_ba, adrs_b_rg, adrs_d_rg,
swap_rg, swap_ba, tile_tex_type, tile_tex_size, palette, odd_t, a_three,
a_twelve, clr_ind_a, clr_ind_b, clr_ind_c, clr_ind_d, red_a,
green_a, blue_a, alpha_a, red_b, green_b, blue_b, alpha_b, red_c, green_c,
blue_c, alpha_c, red_d, green_d, blue_d, alpha_d, copy_load, load_dv,
bist_done, bist0_fail, bist1_fail, bist2_fail, bist3_fail, bist4_fail,
bist5_fail, bist6_fail, bist7_fail);
input gclk; // RDP gated clock
input reset_l; // reset (active low)
input bist_go; // mem test enable
input bist_check; // bist test enable
input iddq; // iddq mode enabled
// attribute data
input tlut_en; // enable texture lookup table
input tlut_type; // tlut type
// from texture coordinate unit
input [7:0] adrs_bnk0l; // sorted address to low bank 0
input [7:0] adrs_bnk1l; // sorted address to low bank 1
input [7:0] adrs_bnk2l; // sorted address to low bank 2
input [7:0] adrs_bnk3l; // sorted address to low bank 3
input [7:0] adrs_bnk0h; // sorted address to high bank 0
input [7:0] adrs_bnk1h; // sorted address to high bank 1
input [7:0] adrs_bnk2h; // sorted address to high bank 2
input [7:0] adrs_bnk3h; // sorted address to high bank 3
input [4:0] adrs_a; // address of texel a <12,3:0>
input [4:0] adrs_b_ba; // address of texel b (ba banks) <12,3:0>
input [4:0] adrs_c; // address of texel c <12,3:0>
input [4:0] adrs_d_ba; // address of texel d (ba banks) <12,3:0>
input [4:0] adrs_b_rg; // address of texel b (rg banks) <12,3:0>
input [4:0] adrs_d_rg; // address of texel d (rg banks) <12,3:0>
input swap_rg; // swap texels (RG)
input swap_ba; // swap texels (BA)
input [2:0] tile_tex_type; // tile texel type
input [1:0] tile_tex_size; // tile texel size
input [3:0] palette; // palette for 4-bit color index
input odd_t; // odd line
input a_three; // address a[3] before interleave
input a_twelve; // address a[12]
// to texture coordinate unit
output [7:0] clr_ind_a; // color index texel a
output [7:0] clr_ind_b; // color index texel b
output [7:0] clr_ind_c; // color index texel c
output [7:0] clr_ind_d; // color index texel d
// to texture filter unit
output [8:0] red_a; // texel a, red / u channel
output [8:0] green_a; // texel a, green / v channel
output [8:0] blue_a; // texel a, blue / y channel
output [8:0] alpha_a; // texel a, alpha / y channel
output [8:0] red_b; // texel b, red / u channel
output [8:0] green_b; // texel b, green / v channel
output [8:0] blue_b; // texel b, blue / y channel
output [8:0] alpha_b; // texel b, alpha / y channel
output [8:0] red_c; // texel c, red / u channel
output [8:0] green_c; // texel c, green / v channel
output [8:0] blue_c; // texel c, blue / y channel
output [8:0] alpha_c; // texel c, alpha / y channel
output [8:0] red_d; // texel d, red / u channel
output [8:0] green_d; // texel d, green / v channel
output [8:0] blue_d; // texel d, blue / y channel
output [8:0] alpha_d; // texel d, alpha / y channel
// to / from memspan unit
inout [63:0] copy_load; // bidirectional copy / load bus
input load_dv; // valid load data on copy_load bus
// other
output bist_done; // bist done
output bist0_fail; // mem test fail flag (active high) (bnk0)
output bist1_fail; // mem test fail flag (active high) (bnk1)
output bist2_fail; // mem test fail flag (active high) (bnk2)
output bist3_fail; // mem test fail flag (active high) (bnk3)
output bist4_fail; // mem test fail flag (active high) (bnk4)
output bist5_fail; // mem test fail flag (active high) (bnk5)
output bist6_fail; // mem test fail flag (active high) (bnk6)
output bist7_fail; // mem test fail flag (active high) (bnk7)
// wires
wire [63:0] di_high; // data_in to high banks
wire [63:0] di_low; // data_in to low banks
wire web01_low; // write enable banks 0,1 (low half)
wire web23_low; // write enable banks 2,3 (low half)
wire web01_high; // write enable banks 0,1 (high half)
wire web23_high; // write enable banks 2,3 (high half)
wire [15:0] dout_bnk0l; // data out bank0 - low half
wire [15:0] dout_bnk1l; // data out bank1 - low half
wire [15:0] dout_bnk2l; // data out bank2 - low half
wire [15:0] dout_bnk3l; // data out bank3 - low half
wire [15:0] dout_bnk0h; // data out bank0 - high half
wire [15:0] dout_bnk1h; // data out bank1 - high half
wire [15:0] dout_bnk2h; // data out bank2 - high half
wire [15:0] dout_bnk3h; // data out bank3 - high half
wire [63:0] copy_bus; // copy bus
wire [7:0] ram0_addr; // address to ram (bnk0)
wire [7:0] ram1_addr; // address to ram (bnk1)
wire [7:0] ram2_addr; // address to ram (bnk2)
wire [7:0] ram3_addr; // address to ram (bnk3)
wire [7:0] ram4_addr; // address to ram (bnk4)
wire [7:0] ram5_addr; // address to ram (bnk5)
wire [7:0] ram6_addr; // address to ram (bnk6)
wire [7:0] ram7_addr; // address to ram (bnk7)
wire [15:0] ram0_din; // data_in to ram (bnk0)
wire [15:0] ram1_din; // data_in to ram (bnk1)
wire [15:0] ram2_din; // data_in to ram (bnk2)
wire [15:0] ram3_din; // data_in to ram (bnk3)
wire [15:0] ram4_din; // data_in to ram (bnk4)
wire [15:0] ram5_din; // data_in to ram (bnk5)
wire [15:0] ram6_din; // data_in to ram (bnk6)
wire [15:0] ram7_din; // data_in to ram (bnk7)
wire ram0_web; // web to ram (bnk0)
wire ram1_web; // web to ram (bnk1)
wire ram2_web; // web to ram (bnk2)
wire ram3_web; // web to ram (bnk3)
wire ram4_web; // web to ram (bnk4)
wire ram5_web; // web to ram (bnk5)
wire ram6_web; // web to ram (bnk6)
wire ram7_web; // web to ram (bnk7)
wire [15:0] sort_tex_a_low; // sorted texel a (low half)
wire [15:0] sort_tex_b_low; // sorted texel b (low half)
wire [15:0] sort_tex_c_low; // sorted texel c (low half)
wire [15:0] sort_tex_d_low; // sorted texel d (low half)
wire [15:0] sort_tex_a_high; // sorted texel a (high half)
wire [15:0] sort_tex_b_high; // sorted texel b (high half)
wire [15:0] sort_tex_c_high; // sorted texel c (high half)
wire [15:0] sort_tex_d_high; // sorted texel d (high half)
wire [4:0] swap_a_low; // swapped address a (low half)
wire [4:0] swap_b_low; // swapped address b (low half)
wire [4:0] swap_c_low; // swapped address c (low half)
wire [4:0] swap_d_low; // swapped address d (low half)
wire [4:0] swap_a_high; // swapped address a (high half)
wire [4:0] swap_b_high; // swapped address b (high half)
wire [4:0] swap_c_high; // swapped address c (high half)
wire [4:0] swap_d_high; // swapped address d (high half)
wire [1:0] tile_tex_size_2d; // tile texel size delayed 2
wire [3:0] palette_1d; // palette delayed 1
wire tlut_en_2d; // tlut_en delayed 2
// instance the tmem load interface
tm_load load (.gclk(gclk), .copy_load(copy_load), .load_dv(load_dv),
.tile_tex_type(tile_tex_type), .tile_tex_size(tile_tex_size),
.odd_t(odd_t), .a_three(a_three), .a_twelve(a_twelve),
.di_high(di_high), .di_low(di_low), .web01_low(web01_low),
.web23_low(web23_low), .web01_high(web01_high),
.web23_high(web23_high));
// instance the tmem bist
ram_bist_tmem bist (.clk(gclk), .reset_l(reset_l), .bist_go(bist_go),
.bist_check(bist_check),
.sys0_addr(adrs_bnk0l), .sys1_addr(adrs_bnk1l),
.sys2_addr(adrs_bnk2l), .sys3_addr(adrs_bnk3l),
.sys4_addr(adrs_bnk0h), .sys5_addr(adrs_bnk1h),
.sys6_addr(adrs_bnk2h), .sys7_addr(adrs_bnk3h),
.sys0_din(di_low[63:48]), .sys1_din(di_low[47:32]),
.sys2_din(di_low[31:16]), .sys3_din(di_low[15:0]),
.sys4_din(di_high[63:48]), .sys5_din(di_high[47:32]),
.sys6_din(di_high[31:16]), .sys7_din(di_high[15:0]),
.sys0_web(web01_low), .sys1_web(web01_low),
.sys2_web(web23_low), .sys3_web(web23_low),
.sys4_web(web01_high), .sys5_web(web01_high),
.sys6_web(web23_high), .sys7_web(web23_high),
.ram0_do(dout_bnk0l), .ram1_do(dout_bnk1l),
.ram2_do(dout_bnk2l), .ram3_do(dout_bnk3l),
.ram4_do(dout_bnk0h), .ram5_do(dout_bnk1h),
.ram6_do(dout_bnk2h), .ram7_do(dout_bnk3h),
.ram0_addr(ram0_addr), .ram1_addr(ram1_addr),
.ram2_addr(ram2_addr), .ram3_addr(ram3_addr),
.ram4_addr(ram4_addr), .ram5_addr(ram5_addr),
.ram6_addr(ram6_addr), .ram7_addr(ram7_addr),
.ram0_din(ram0_din), .ram1_din(ram1_din),
.ram2_din(ram2_din), .ram3_din(ram3_din),
.ram4_din(ram4_din), .ram5_din(ram5_din),
.ram6_din(ram6_din), .ram7_din(ram7_din),
.ram0_web(ram0_web), .ram1_web(ram1_web),
.ram2_web(ram2_web), .ram3_web(ram3_web),
.ram4_web(ram4_web), .ram5_web(ram5_web),
.ram6_web(ram6_web), .ram7_web(ram7_web),
.bist_done(bist_done),
.bist0_fail(bist0_fail), .bist1_fail(bist1_fail),
.bist2_fail(bist2_fail), .bist3_fail(bist3_fail),
.bist4_fail(bist4_fail), .bist5_fail(bist5_fail),
.bist6_fail(bist6_fail), .bist7_fail(bist7_fail));
// instance the 8 texture memory banks
tm_half low_half (.gclk(gclk), .iddq(iddq), .ram0_addr(ram0_addr),
.ram1_addr(ram1_addr), .ram2_addr(ram2_addr),
.ram3_addr(ram3_addr), .ram0_web(ram0_web),
.ram1_web(ram1_web), .ram2_web(ram2_web),
.ram3_web(ram3_web), .ram0_din(ram0_din),
.ram1_din(ram1_din), .ram2_din(ram2_din),
.ram3_din(ram3_din), .ram0_dout(dout_bnk0l),
.ram1_dout(dout_bnk1l), .ram2_dout(dout_bnk2l),
.ram3_dout(dout_bnk3l));
tm_half hi_half (.gclk(gclk), .iddq(iddq), .ram0_addr(ram4_addr),
.ram1_addr(ram5_addr), .ram2_addr(ram6_addr),
.ram3_addr(ram7_addr), .ram0_web(ram4_web),
.ram1_web(ram5_web), .ram2_web(ram6_web),
.ram3_web(ram7_web), .ram0_din(ram4_din),
.ram1_din(ram5_din), .ram2_din(ram6_din),
.ram3_din(ram7_din), .ram0_dout(dout_bnk0h),
.ram1_dout(dout_bnk1h), .ram2_dout(dout_bnk2h),
.ram3_dout(dout_bnk3h));
// instance the texture memory mux modules
tm_mux1 mux1 (.gclk(gclk), .swap_rg(swap_rg), .swap_ba(swap_ba),
.adrs_a(adrs_a), .adrs_b_ba(adrs_b_ba), .adrs_c(adrs_c),
.adrs_d_ba(adrs_d_ba), .adrs_b_rg(adrs_b_rg),
.adrs_d_rg(adrs_d_rg), .dout_bnk0l(dout_bnk0l),
.dout_bnk1l(dout_bnk1l), .dout_bnk2l(dout_bnk2l),
.dout_bnk3l(dout_bnk3l), .dout_bnk0h(dout_bnk0h),
.dout_bnk1h(dout_bnk1h), .dout_bnk2h(dout_bnk2h),
.dout_bnk3h(dout_bnk3h), .tlut_en(tlut_en),
.tile_tex_size(tile_tex_size), .palette(palette),
//
.sort_tex_a_low_buf(sort_tex_a_low), .sort_tex_b_low_buf(sort_tex_b_low),
.sort_tex_c_low_buf(sort_tex_c_low), .sort_tex_d_low_buf(sort_tex_d_low),
.sort_tex_a_high_buf(sort_tex_a_high), .sort_tex_b_high_buf(sort_tex_b_high),
.sort_tex_c_high_buf(sort_tex_c_high), .sort_tex_d_high_buf(sort_tex_d_high),
.swap_a_low_buf(swap_a_low), .swap_b_low_buf(swap_b_low),
.swap_c_low_buf(swap_c_low), .swap_d_low_buf(swap_d_low),
.swap_a_high_buf(swap_a_high), .swap_b_high_buf(swap_b_high),
.swap_c_high_buf(swap_c_high), .swap_d_high_buf(swap_d_high),
.clr_ind_a_buf(clr_ind_a), .clr_ind_b_buf(clr_ind_b),
.clr_ind_c_buf(clr_ind_c), .clr_ind_d_buf(clr_ind_d),
.tile_tex_size_2d_buf(tile_tex_size_2d), .palette_1d_buf(palette_1d),
.tlut_en_2d_buf(tlut_en_2d));
tm_mux2 mux2 (.gclk(gclk), .tlut_type(tlut_type), .tile_tex_type(tile_tex_type),
.tile_tex_size_2d(tile_tex_size_2d), .palette_1d(palette_1d),
.tlut_en_2d(tlut_en_2d), .swap_a_low(swap_a_low), .swap_b_low(swap_b_low),
.swap_c_low(swap_c_low), .swap_d_low(swap_d_low), .swap_a_high(swap_a_high),
.swap_b_high(swap_b_high), .swap_c_high(swap_c_high), .swap_d_high(swap_d_high),
.sort_tex_a_low(sort_tex_a_low), .sort_tex_b_low(sort_tex_b_low),
.sort_tex_c_low(sort_tex_c_low), .sort_tex_d_low(sort_tex_d_low),
.sort_tex_a_high(sort_tex_a_high), .sort_tex_b_high(sort_tex_b_high),
.sort_tex_c_high(sort_tex_c_high),
.sort_tex_d_high(sort_tex_d_high), .copy_bus(copy_bus),
.red_a(red_a), .red_b(red_b), .red_c(red_c),
.red_d(red_d), .green_a(green_a), .green_b(green_b),
.green_c(green_c), .green_d(green_d), .blue_a(blue_a),
.blue_b(blue_b), .blue_c(blue_c), .blue_d(blue_d),
.alpha_a(alpha_a), .alpha_b(alpha_b),
.alpha_c(alpha_c), .alpha_d(alpha_d));
// copy_load bus
tm_tbuf64 copy_load_bufs (.z(copy_load), .i(copy_bus), .oen(load_dv));
endmodule // tm
module tm_tbuf64 (z, i, oen);
input [63:0] i;
input oen;
output [63:0] z;
wire oe;
assign oe = ~oen;
nt01d3 b0 (.i(i[0]), .z(z[0]), .oe(oe));
nt01d3 b1 (.i(i[1]), .z(z[1]), .oe(oe));
nt01d3 b2 (.i(i[2]), .z(z[2]), .oe(oe));
nt01d3 b3 (.i(i[3]), .z(z[3]), .oe(oe));
nt01d3 b4 (.i(i[4]), .z(z[4]), .oe(oe));
nt01d3 b5 (.i(i[5]), .z(z[5]), .oe(oe));
nt01d3 b6 (.i(i[6]), .z(z[6]), .oe(oe));
nt01d3 b7 (.i(i[7]), .z(z[7]), .oe(oe));
nt01d3 b8 (.i(i[8]), .z(z[8]), .oe(oe));
nt01d3 b9 (.i(i[9]), .z(z[9]), .oe(oe));
nt01d3 b10 (.i(i[10]), .z(z[10]), .oe(oe));
nt01d3 b11 (.i(i[11]), .z(z[11]), .oe(oe));
nt01d3 b12 (.i(i[12]), .z(z[12]), .oe(oe));
nt01d3 b13 (.i(i[13]), .z(z[13]), .oe(oe));
nt01d3 b14 (.i(i[14]), .z(z[14]), .oe(oe));
nt01d3 b15 (.i(i[15]), .z(z[15]), .oe(oe));
nt01d3 b16 (.i(i[16]), .z(z[16]), .oe(oe));
nt01d3 b17 (.i(i[17]), .z(z[17]), .oe(oe));
nt01d3 b18 (.i(i[18]), .z(z[18]), .oe(oe));
nt01d3 b19 (.i(i[19]), .z(z[19]), .oe(oe));
nt01d3 b20 (.i(i[20]), .z(z[20]), .oe(oe));
nt01d3 b21 (.i(i[21]), .z(z[21]), .oe(oe));
nt01d3 b22 (.i(i[22]), .z(z[22]), .oe(oe));
nt01d3 b23 (.i(i[23]), .z(z[23]), .oe(oe));
nt01d3 b24 (.i(i[24]), .z(z[24]), .oe(oe));
nt01d3 b25 (.i(i[25]), .z(z[25]), .oe(oe));
nt01d3 b26 (.i(i[26]), .z(z[26]), .oe(oe));
nt01d3 b27 (.i(i[27]), .z(z[27]), .oe(oe));
nt01d3 b28 (.i(i[28]), .z(z[28]), .oe(oe));
nt01d3 b29 (.i(i[29]), .z(z[29]), .oe(oe));
nt01d3 b30 (.i(i[30]), .z(z[30]), .oe(oe));
nt01d3 b31 (.i(i[31]), .z(z[31]), .oe(oe));
nt01d3 b32 (.i(i[32]), .z(z[32]), .oe(oe));
nt01d3 b33 (.i(i[33]), .z(z[33]), .oe(oe));
nt01d3 b34 (.i(i[34]), .z(z[34]), .oe(oe));
nt01d3 b35 (.i(i[35]), .z(z[35]), .oe(oe));
nt01d3 b36 (.i(i[36]), .z(z[36]), .oe(oe));
nt01d3 b37 (.i(i[37]), .z(z[37]), .oe(oe));
nt01d3 b38 (.i(i[38]), .z(z[38]), .oe(oe));
nt01d3 b39 (.i(i[39]), .z(z[39]), .oe(oe));
nt01d3 b40 (.i(i[40]), .z(z[40]), .oe(oe));
nt01d3 b41 (.i(i[41]), .z(z[41]), .oe(oe));
nt01d3 b42 (.i(i[42]), .z(z[42]), .oe(oe));
nt01d3 b43 (.i(i[43]), .z(z[43]), .oe(oe));
nt01d3 b44 (.i(i[44]), .z(z[44]), .oe(oe));
nt01d3 b45 (.i(i[45]), .z(z[45]), .oe(oe));
nt01d3 b46 (.i(i[46]), .z(z[46]), .oe(oe));
nt01d3 b47 (.i(i[47]), .z(z[47]), .oe(oe));
nt01d3 b48 (.i(i[48]), .z(z[48]), .oe(oe));
nt01d3 b49 (.i(i[49]), .z(z[49]), .oe(oe));
nt01d3 b50 (.i(i[50]), .z(z[50]), .oe(oe));
nt01d3 b51 (.i(i[51]), .z(z[51]), .oe(oe));
nt01d3 b52 (.i(i[52]), .z(z[52]), .oe(oe));
nt01d3 b53 (.i(i[53]), .z(z[53]), .oe(oe));
nt01d3 b54 (.i(i[54]), .z(z[54]), .oe(oe));
nt01d3 b55 (.i(i[55]), .z(z[55]), .oe(oe));
nt01d3 b56 (.i(i[56]), .z(z[56]), .oe(oe));
nt01d3 b57 (.i(i[57]), .z(z[57]), .oe(oe));
nt01d3 b58 (.i(i[58]), .z(z[58]), .oe(oe));
nt01d3 b59 (.i(i[59]), .z(z[59]), .oe(oe));
nt01d3 b60 (.i(i[60]), .z(z[60]), .oe(oe));
nt01d3 b61 (.i(i[61]), .z(z[61]), .oe(oe));
nt01d3 b62 (.i(i[62]), .z(z[62]), .oe(oe));
nt01d3 b63 (.i(i[63]), .z(z[63]), .oe(oe));
endmodule