/*****************************************************************
     * NORM state 
     *****************************************************************/
    #4;	ad16_data_in = 15'h0;
        ad16_enable_l = 0;
        ad16_read_l = 0;
        ad16_write_l = 0;
        bist_flag = 1;                  repeat (1) @(posedge clk);
        test = 0; pad_reset_l = 1; 	repeat (1) @(posedge clk);

    #4; reset;				repeat (4) @(posedge clk);
    #4; test = 1;			repeat (2) @(posedge clk);

    /*****************************************************************
     * MUX state 
     *****************************************************************/

    repeat (4) @(posedge clk);

    #4; next_state; 			repeat (4) @(posedge clk);

    #4; ad16_data_in = 15'h0000;	repeat (1) @(posedge clk);
    #4; ad16_data_in = 15'h4000;	repeat (1) @(posedge clk);
    #4; ad16_data_in = 15'h0000;	repeat (1) @(posedge clk);
    #4; ad16_data_in = 15'h4000;	repeat (1) @(posedge clk);
    #4; ad16_data_in = 15'h0000;	repeat (1) @(posedge clk);
    #4; ad16_data_in = 15'h4000;	repeat (1) @(posedge clk);
    #4; ad16_data_in = 15'h0000;	repeat (1) @(posedge clk);