/* read the verilog sources */

search_path = search_path + "../../syn"

read -f verilog ../src/tst.v

current_design = tst

ungroup -flatten u_*
dont_touch u_*

set_operating_conditions NOM
set_wire_load 128000 -mode top



link 

check_design > tst.lint

report -reference

report_constraint -all_violators

report -net > tst.rn

write -f edif -o tst.edf -hier tst

set_arrival 0 ad16_data_in[14];
report_timing -path full -from ad16_data_in[14];

include tst.tmg
include report.dc

quit