rnumdec.ss
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/* setup aliases */
alias set_default_operating_conditions \
"set_operating_conditions NOM -library rcp.db; \
set_wire_load 256000 -mode top;"
alias set_default_timing_constraints \
"create_clock clk -period 16.0 -waveform {0 8.0}; \
set_input_delay 13.0 -clock clk all_inputs(); \
set_input_delay 7.0 clk; \
set_clock_skew -uncertainty 1 clk; \
fix_hold clk; \
dont_touch_network clk; \
set_output_delay -max 14.0 -clock clk all_outputs(); \
set_driving_cell -none {clk}; \
set_driving_cell -cell in01d1 all_inputs(); \
set_drive 0 {clk}; \
set_load 1.0 all_outputs();"
/* setup the search path for includes */
search_path = search_path + "../src"
/* read the verilog sources */
read -f verilog ../src/rnumdec.v
read -f edif regfile_decode.edf
read -f verilog ../../rsp/src/rsp_lden32_f.v
read -f verilog ../../rsp/src/rsp_lden32_t.v
read -f verilog ../../../lib/verilog/user/asdff.v
read -f verilog ../../../lib/verilog/user/asdffen.v
current_design = rnumdec
set_default_operating_conditions
set_default_timing_constraints
max_area 500
set_max_transition 2.0 current_design;
include rnumdec.con
link
check_design > rnumdec.lint
compile -map_effort high -ungroup_all -boundary_optimization
compile -map_effort high -ungroup_all -boundary_optimization
write -f edif -o rnumdec1.edf -hier rnumdec
report -reference > report/rnumdec1.ref
report_constraint -all_violators > report/rnumdec1.violators
report_timing -path full -delay max -max_paths 10 > report/rnumdec1.full.paths
report_area > report/rnumdec1.area
remove_attribute find(cell, "vctxposeadd1rd") dont_touch
remove_attribute find(cell, "vctxposeadd2rd") dont_touch
remove_attribute find(cell, "vctxposemx0rd") dont_touch
remove_attribute find(cell, "vctxposemx1rd") dont_touch
remove_attribute find(cell, "vctxposemx2rd") dont_touch
remove_attribute find(cell, "vctxposemx3rd") dont_touch
remove_attribute find(cell, "vctxposemx4rd") dont_touch
remove_attribute find(cell, "vctloadadd0rd") dont_touch
remove_attribute find(cell, "vctloadadd1rd") dont_touch
remove_attribute find(cell, "vctloadadd2rd") dont_touch
remove_attribute find(cell, "vctloadmx0rd") dont_touch
remove_attribute find(cell, "vctloadmx1rd") dont_touch
remove_attribute find(cell, "vctloadmx2rd") dont_touch
compile -map_effort high -ungroup_all -incremental_mapping -boundary_optimization
compile -map_effort high -ungroup_all -incremental_mapping -boundary_optimization
write -f edif -o rnumdec2.edf -hier rnumdec
report -reference > report/rnumdec2.ref
report_constraint -all_violators > report/rnumdec2.violators
report_timing -path full -delay max -max_paths 10 > report/rnumdec2.full.paths
report_area > report/rnumdec2.area
compile -map_effort high -ungroup_all -incremental_mapping -boundary_optimization
compile -map_effort high -ungroup_all -incremental_mapping -boundary_optimization
write -f edif -o rnumdec.edf -hier rnumdec
report -reference > report/rnumdec.ref
report_constraint -all_violators > report/rnumdec.violators
report_timing -path full -delay max -max_paths 10 > report/rnumdec.full.paths
report_area > report/rnumdec.area
quit