vurfctl.ss
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/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 256000 -mode top;"
alias set_default_timing_constraints "create_clock clk -period 16 -waveform {0 8}; \
set_input_delay 15.0 -clock clk all_inputs(); \
set_clock_skew -uncertainty 1 clk; \
dont_touch_network clk; \
set_output_delay -max 14.5 -clock clk all_outputs(); \
set_driving_cell -cell in01d2 all_inputs(); \
set_drive 0 {clk}; \
set_load 2.0 all_outputs();"
/* setup the search path for includes */
search_path = search_path + "../src"
/* read the verilog sources */
read -f verilog ../src/vurfctl.v
read -f verilog ../../../lib/verilog/user/asdff.v
read -f verilog ../../../lib/verilog/user/asdffen.v
current_design = vurfctl
set_default_operating_conditions
set_default_timing_constraints
max_area 500
set_max_fanout 1 current_design;
set_max_fanout 0.25 all_inputs();
set_max_transition 2.0 current_design;
set_max_transition 0.50 all_inputs();
set_max_transition 0.50 all_outputs();
current_design = vurfctl
include vurfctl.con
current_design = vurfctl
link
check_design > vurfctl_pre.lint
ungroup -flatten -all
compile -map_effort high -boundary_optimization
check_design > vurfctl_post.lint
write -f edif -o vurfctl_1st.edf -hier vurfctl
write -f db -o vurfctl_1st.db -hier vurfctl
report_timing -path full -delay max -max_paths 10 > report/vurfctl_1st.full.paths
report_net > report/vurfctl_1st.net
report_constraint -all_violators > report/vurfctl_1st.violators
report -reference > report/vurfctl_1st.ref
report_area > report/vurfctl_1st.area
compile -map_effort high -boundary_optimization -incremental_mapping
write -f edif -o vurfctl.edf -hier vurfctl
write -f db -o vurfctl.db -hier vurfctl
report_timing -path full -delay max -max_paths 10 > report/vurfctl.full.paths
report_net > report/vurfctl.net
report_constraint -all_violators > report/vurfctl.violators
write -f db -o vurfctl.db -hier vurfctl
report -reference > report/vurfctl.ref
report_area > report/vurfctl.area
quit