vusl.ss
4.92 KB
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/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 256000 -mode top;"
alias set_default_timing_constraints "create_clock clk -period 16 -waveform {0 8}; \
set_input_delay 15.0 -clock clk all_inputs(); \
set_clock_skew -uncertainty 1 clk; \
dont_touch_network clk; \
set_output_delay -max 14.5 -clock clk all_outputs(); \
set_driving_cell -cell in01d0 all_inputs(); \
set_drive 0 {clk}; \
set_load 2.0 all_outputs();"
/* setup the search path for includes */
search_path = search_path + "../src"
/* read the verilog sources */
read -f verilog ../src/dp_buf16.v
read -f verilog ../src/dp_adder16.v
read -f verilog ../src/dp_adder32.v
read -f verilog ../src/dp_csa32.v
read -f verilog ../src/dp_incdec16.v
read -f verilog ../src/dp_2to1mx16.v
read -f verilog ../src/dp_4to1mx16.v
read -f verilog ../src/dp_8to1mx16.v
read -f verilog ../src/dp_reg16.v
read -f verilog ../src/dp_regmx16.v
read -f verilog ../src/dp_regmx16hp.v
read -f verilog ../src/dp_zerodet.v
read -f verilog ../src/dp_onedet.v
read -f verilog ../src/dp_tribuf16.v
read -f verilog ../src/vudp_nonrf.v
read -f verilog ../src/vmult.v
read -f verilog ../src/vulca.v
read -f verilog ../src/vuctlsl.v
read -f verilog ../src/vuctl.v
read -f verilog ../src/vusl.v
/* read -f edif rnumdec.edf */
read -f verilog ../../../lib/verilog/user/asdff.v
read -f verilog ../../../lib/verilog/user/asdffen.v
current_design = vusl
set_default_operating_conditions
set_default_timing_constraints
max_area 60000
/* compile_no_new_cells_at_top_level = "true" */
set_max_fanout 1 current_design;
set_max_fanout 0.25 all_inputs();
set_max_transition 2.0 current_design;
set_max_transition 0.25 all_inputs();
set_max_transition 0.5 all_outputs();
/* set_disable_timing su_cont_to_from */
current_design = vusl
include vusl.con
current_design = vusl
link
check_design > vusl_pre.lint
uniquify -force
compile -map_effort high -boundary_optimization
report_timing -path full -delay max -max_paths 10 > report/vusl_1st.full.paths
check_design > vusl_post.lint
write -f edif -o vusl_1st.edf -hier vusl
/* write -f edif -o vusl.edf -hier vusl */
write -f db -o vusl_1st.db -hier vusl
/* write -f db -o vusl.db -hier vusl */
/* write -f verilog -o vusl.vsyn {vusl, vuctl, vmult} */
report_net > report/vusl_1st.net
report_constraint -all_violators > report/vusl_1st.violators
/*
remove_attribute find(reference, "buf_16bit") dont_touch
remove_attribute find(reference, "dp_adder16") dont_touch
remove_attribute find(reference, "dp_adder32") dont_touch
remove_attribute find(reference, "dp_csa32") dont_touch
remove_attribute find(reference, "dp_incdec_16bit") dont_touch
remove_attribute find(reference, "mx_16bit_2to1") dont_touch
remove_attribute find(reference, "mx_16bit_4to1") dont_touch
remove_attribute find(reference, "mx_16bit_8to1") dont_touch
remove_attribute find(reference, "regmx_16bit") dont_touch
remove_attribute find(reference, "tribuf_16bit") dont_touch
remove_attribute find(reference, "rf_memory_cell") dont_touch
remove_attribute find(reference, "address_buf*") dont_touch
ungroup -flatten -all
*/
report -reference > report/vusl_1st.ref
report_area > report/vusl_1st.area
current_design = vuctl
remove_attribute find(cell, "vctcontbusmx0mu") dont_touch
remove_attribute find(cell, "vctcontbusmx1mu") dont_touch
remove_attribute find(cell, "vctcontbusmx2mu") dont_touch
remove_attribute find(cell, "vctcontbusmx3mu") dont_touch
remove_attribute find(cell, "vctcontbusin0mu") dont_touch
remove_attribute find(cell, "vctcontbusin1mu") dont_touch
current_design = vusl
compile -map_effort high -boundary_optimization -incremental_mapping
write -f edif -o vusl_2nd.edf -hier vusl
write -f db -o vusl_2nd.db -hier vusl
report_timing -path full -delay max -max_paths 10 > report/vusl_2nd.full.paths
report_net > report/vusl_2nd.net
report_constraint -all_violators > report/vusl_2nd.violators
report -reference > report/vusl_2nd.ref
report_area > report/vusl_2nd.area
set_disable_timing su_cont_to_from
set_driving_cell -cell in01d1 su_cont_to_from
compile -map_effort high -boundary_optimization -incremental_mapping
write -f edif -o vusl_3rd.edf -hier vusl
write -f db -o vusl_3rd.db -hier vusl
report_timing -path full -delay max -max_paths 10 > report/vusl_3rd.full.paths
report_net > report/vusl_3rd.net
report_constraint -all_violators > report/vusl_3rd.violators
report -reference > report/vusl_3rd.ref
report_area > report/vusl_3rd.area
compile -map_effort high -boundary_optimization -incremental_mapping
compile -map_effort high -boundary_optimization -incremental_mapping
write -f edif -o vusl.edf -hier vusl
write -f db -o vusl.db -hier vusl
report_timing -path full -delay max -max_paths 10 > report/vusl.full.paths
report_net > report/vusl.net
report_constraint -all_violators > report/vusl.violators
report -reference > report/vusl.ref
report_area > report/vusl.area
quit