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/************************************************************************
TOP-LEVEL MIXED TRAFFIC RSP DMA TESTS: File #0
************************************************************************/
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Start: ori $4, $0, 0xC000 /* reg initialization */
ori $5, $0, 0xC000 /* reg initialization */
ori $6, $0, 0xC000 /* reg initialization */
ori $7, $0, 0xC000 /* reg initialization */
ori $8, $0, 0xC000 /* reg initialization */
ori $9, $0, 0xC000 /* reg initialization */
ori $10, $0, 0xC000 /* reg initialization */
ori $11, $0, 0xC000 /* reg initialization */
ori $20, $0, 0xC000 /* reg initialization */
ori $21, $0, 0xC000 /* reg initialization */
ori $22, $0, 0xC000 /* reg initialization */
ori $23, $0, 0xC000 /* reg initialization */
ori $24, $0, 0xC000 /* reg initialization */
ori $25, $0, 0xC000 /* reg initialization */
ori $26, $0, 0xC000 /* reg initialization */
ori $27, $0, 0xC000 /* reg initialization */
/****************************************************************
DMA TEST #0.0
****************************************************************/
/* XBUS Ring-Buffer test */
or $1, $0, $0 /* R1 = TEST ID */
mfc0 $2, $4 /* read SP Status Reg */
andi $2, $2, 0x0040 /* extract signal 0 */
beq $2, $0, Skip /* CPU not requesting */
CmdWait: mfc0 $2, $11 /* read DPC Status Reg */
andi $2, $2, 0x0200 /* extract end valid */
bne $2, $0, CmdWait /* wait for XBUS idle */
ori $2, $0, 0x0002 /* set xbus_dmem_dma b */
mtc0 $2, $11 /* write DP status reg */
lui $2, 0x0400 /* load start address */
ori $2, $2, 0x0800
mtc0 $2, $8 /* write start address */
addi $2, $2, 0x0070 /* prep end address */
mtc0 $2, $9 /* write end address */
addi $2, $2, 0x0058 /* prep end address */
mtc0 $2, $9 /* write end address */
addi $2, $2, 0x0028 /* prep end address */
mtc0 $2, $9 /* write end address */
addi $2, $2, 0x0008 /* prep end address */
mtc0 $2, $9 /* write end address */
ori $2, $0, 0x2A80 /* clear all signals */
mtc0 $2, $4
Skip:
/****************************************************************
DMA TEST #0.1
****************************************************************/
ori $1, $0, 0x0001 /* R1 = TEST ID */
ori $12, $0, 0x1580 /* R12 = IMEM address */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x5000
ori $14, $0, 0x027F /* R14 = read length */
jal DmaRead /* go start DMA */
nop
jal DoSubr /* go do smthn, anythn */
ori $2, $0, 0x0008 /* idle 8 times */
jal DmaDone /* wait till DMA done */
nop
jal L0580 /* exec IMEM code */
nop
jal ICheck /* check exec result */
nop
/****************************************************************
DMA TEST #0.2
****************************************************************/
ori $1, $0, 0x0002 /* R1 = TEST ID */
ori $12, $0, 0x1580 /* R12 = IMEM address */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x6000
ori $14, $0, 0x0007 /* R14 = read length */
addi $20, $20, 0x0001 /* answer */
addi $21, $21, 0x0001 /* answer */
jal DmaRead /* go start DMA */
nop
jal DoSubr /* go do smthn, anythn */
ori $2, $0, 0x0002 /* idle 2 times */
jal DmaDone /* wait till DMA done */
nop
jal L0580 /* exec IMEM code */
nop
jal ICheck /* check exec result */
nop
/****************************************************************
DMA TEST #0.3
****************************************************************/
ori $1, $0, 0x0003 /* R1 = TEST ID */
ori $12, $0, 0x0580 /* R12 = DMEM address */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x2000
lui $14, 0x0080 /* R14 = read length */
ori $14, $14, 0x0017
sw $1, 0x0598 ($0) /* prevent overwrite */
jal DmaRead /* go start DMA */
nop
jal DoSubr /* go do smthn, anythn */
ori $2, $0, 0x0002 /* idle 2 times */
jal DmaDone /* wait till DMA done */
nop
jal DCheck /* check DMEM data */
nop
/****************************************************************
DMA TEST #0.4
****************************************************************/
ori $1, $0, 0x0004 /* R1 = TEST ID */
ori $12, $0, 0x1580 /* R12 = IMEM address */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x6008
ori $14, $0, 0x000F /* R14 = read length */
addi $22, $22, 0x0001 /* answer */
addi $23, $23, 0x0001 /* answer */
addi $24, $24, 0x0001 /* answer */
addi $25, $25, 0x0001 /* answer */
jal DmaRead /* go start DMA */
nop
jal DoSubr /* go do smthn, anythn */
ori $2, $0, 0x0002 /* idle 2 times */
jal DmaDone /* wait till DMA done */
nop
jal L0580 /* exec IMEM code */
nop
jal ICheck /* check exec result */
nop
/****************************************************************
DMA TEST #0.5
****************************************************************/
ori $1, $0, 0x0005 /* R1 = TEST ID */
ori $12, $0, 0x0580 /* R12 = DMEM address */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x2000
lui $14, 0x0080 /* R14 = read length */
ori $14, $14, 0x2017
sw $1, 0x05C8 ($0) /* prevent overwrite */
jal DmaRead /* go start DMA */
nop
jal DoSubr /* go do smthn, anythn */
ori $2, $0, 0x0002 /* idle 2 times */
jal DmaDone /* wait till DMA done */
nop
jal DCheck /* check DMEM data */
nop
/****************************************************************
DMA TEST #0.6
****************************************************************/
ori $1, $0, 0x0006 /* R1 = TEST ID */
ori $12, $0, 0x1580 /* R12 = IMEM address */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x6010
ori $14, $0, 0x0017 /* R14 = read length */
addi $20, $20, 0x0001 /* answer */
addi $21, $21, 0x0001 /* answer */
addi $24, $24, 0x0001 /* answer */
addi $25, $25, 0x0001 /* answer */
addi $26, $26, 0x0001 /* answer */
addi $27, $27, 0x0001 /* answer */
jal DmaRead /* go start DMA */
nop
jal DoSubr /* go do smthn, anythn */
ori $2, $0, 0x0002 /* idle 2 times */
jal DmaDone /* wait till DMA done */
nop
jal L0580 /* exec IMEM code */
nop
jal ICheck /* check exec result */
nop
/****************************************************************
DMA TEST #0.7
****************************************************************/
ori $1, $0, 0x0007 /* R1 = TEST ID */
ori $12, $0, 0x0600 /* R12 = DMEM address */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x4000
lui $14, 0x0080 /* R15 = read length */
ori $14, $14, 0x2017
jal DmaRead /* go start DMA */
sw $1, 0x0648 ($0) /* prevent overwrite */
jal DmaDone /* wait till DMA done */
nop
jal DCheck /* check DMEM data */
nop
ori $12, $0, 0x0580 /* R12 = DMEM address */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x2000
jal DmaRead /* go start DMA */
nop
lui $13, 0x0013 /* R13 = new DRAM addr */
ori $13, $13, 0x4000
or $15, $14, $0 /* R15 = write length */
jal DmaWrite /* go start DMA */
nop
jal DmaRead /* read data back */
sw $1, 0x05C8 ($0) /* prevent overwrite */
jal DoSubr /* go do smthn, anythn */
ori $2, $0, 0x0002 /* idle 2 times */
jal DmaDone /* wait till DMA done */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x2000
jal DCheck /* check DMEM data */
nop
ori $12, $0, 0x0580 /* R12 = DMEM address */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x4058
lui $14, 0x0080 /* R15 = read length */
ori $14, $14, 0x000F
jal DmaRead /* go start DMA */
sw $1, 0x0590 ($0) /* prevent over-read */
jal DoSubr /* go do smthn, anythn */
ori $2, $0, 0x0001 /* idle 2 times */
jal DmaDone /* wait till DMA done */
nop
jal DCheck /* check DMEM data */
nop
ori $12, $0, 0x0580 /* R12 = DMEM address */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x4018
lui $14, 0x0180 /* R15 = read length */
ori $14, $14, 0x2007
jal DmaRead /* go start DMA */
sw $1, 0x0598 ($0) /* prevent over-read */
jal DoSubr /* go do smthn, anythn */
ori $2, $0, 0x0001 /* idle 2 times */
jal DmaDone /* wait till DMA done */
nop
jal DCheck /* check DMEM data */
nop
ori $12, $0, 0x0600 /* R12 = DMEM address */
lui $13, 0x0013 /* R13 = DRAM address */
ori $13, $13, 0x4000
lui $14, 0x0080 /* R15 = read length */
ori $14, $14, 0x2017
jal DmaWrite /* go start DMA */
or $15, $14, $0
j Done /* test completed */
nop
/****************************************************************
Subroutines ...
****************************************************************/
/* DMEM DMA CHECK SUBROUTINE */
DCheck:
addi $3, $0, 0x0004 /* init R3 = 4 */
andi $16, $14, 0x0FFF /* len of data (bytes) */
addi $16, $16, 0x0001 /* add 1 to length */
srl $17, $14, 0x000C /* number of spans */
andi $17, $17, 0x00FF
srl $18, $14, 0x0014 /* number of skips */
andi $19, $13, 0xFFFF /* load expected data */
Chk: lw $29, 0x0000 ($12) /* read test data */
bne $29, $19, Fail /* verify data */
sub $16, $16, $3 /* decrement counter */
add $19, $19, $3 /* predict next data */
add $12, $12, $3 /* advance DMEM ptr */
bne $16, $0, Chk /* check if done */
nop /* bne delay slot */
beq $17, $0, DC_done /* exit if zero span */
andi $16, $14, 0x0FFF /* reload len (bytes) */
addi $16, $16, 0x0001 /* reload len (bytes) */
add $19, $19, $18 /* adjust predict data */
addi $17, $17, 0xFFFF /* decrement span cnt */
j Chk /* continue with next */
nop /* bne delay slot */
DC_done: lw $29, 0x0000 ($12) /* read test data */
bne $29, $1, Fail /* check for overflow */
nop /* bne delay slot */
jr $31 /* return to caller */
nop
/* IMEM DMA CHECK SUBROUTINE */
ICheck:
bne $20, $4, Fail /* check $4 */
nop
bne $21, $5, Fail /* check $5 */
nop
bne $22, $6, Fail /* check $6 */
nop
bne $23, $7, Fail /* check $7 */
nop
bne $24, $8, Fail /* check $8 */
nop
bne $25, $9, Fail /* check $9 */
nop
bne $26, $10, Fail /* check $10 */
nop
bne $27, $11, Fail /* check $11 */
nop
jr $31 /* return to caller */
nop
/* IDLING WHILE DMA SUBROUTINE */
DoSubr:
ori $28, $0, 0x3A5A /* init R28 = 0x3A5A */
beq $0, $0, Skip1
add $3, $1, $0 /* start with any num */
Skip1: bne $3, $1, Skip2
add $3, $3, $28 /* add 0x3A5A */
Skip2: j Skip3
sll $3, $3, 0x0002 /* multiply by 4 */
Skip3: sub $3, $0, $3 /* take the neg */
beq $0, $0, Skip4
Skip4: add $3, $3, $1 /* add original num x2 */
bne $3, $0, Skip5
sw $3, 0x0000 ($0)
Skip5: lw $3, 0x0000 ($0)
sub $3, $0, $3 /* take the neg again */
srl $3, $3, 0x0001 /* divide by 2 */
sw $3, 0x0000 ($0)
beq $3, $3, Skip6
lw $3, 0x0000 ($0)
Skip6: beq $3, $3, Skip7
Skip7: sub $3, $3, $28 /* subtract 0x3A5A */
bne $3, $1, Fail /* better get back R1 */
nop
bne $2, $0, DoSubr /* loop n-times as req */
addi $2, $2, 0xFFFF
jr $31 /* return to caller */
nop
/* DMA READ ISSUE SUBROUTINE */
DmaRead:
mfc0 $17, $7 /* request DMA rsrc */
bne $17, $0, DmaRead /* loop */
nop
DR_full:
mfc0 $17, $5 /* check not full */
bne $17, $0, DR_full
nop
mtc0 $12, $0 /* init I/DMEM address */
mtc0 $13, $1 /* init DRAM address */
mtc0 $14, $2 /* init read length */
mtc0 $17, $7 /* release DMA rsrc */
jr $31 /* return to caller */
nop
/* DMA WRITE ISSUE SUBROUTINE */
DmaWrite:
mfc0 $17, $7 /* request DMA rsrc */
bne $17, $0, DmaWrite /* loop */
nop
DW_full:
mfc0 $17, $5 /* check not full */
bne $17, $0, DW_full
nop
mtc0 $12, $0 /* init I/DMEM address */
mtc0 $13, $1 /* init DRAM address */
mtc0 $15, $3 /* init write length */
mtc0 $17, $7 /* release DMA rsrc */
jr $31 /* return to caller */
nop
/* DMA DONE CHECK SUBROUTINE */
DmaDone:
mfc0 $17, $7 /* secure DMA resource */
bne $17, $0, DmaDone
nop
DmaWait:
mfc0 $17, $6 /* wait till not busy */
bne $17, $0, DmaWait
nop
mtc0 $17, $7 /* release DMA rsrc */
jr $31 /* return to caller */
nop
/****************************************************************
Wrap up ...
****************************************************************/
Done: ori $1, $0, 0xFEED /* Test passed */
ori $2, $0, 0x2A00 /* clear sig1-3 */
mtc0 $2, $4
break
j Start
nop
Fail: ori $2, $0, 0x2A00 /* clear sig1-3 */
mtc0 $2, $4
andi $2, $1, 0x0004 /* set sig_3 */
sll $2, $2, 0x000C
mtc0 $2, $4
andi $2, $1, 0x0002 /* set sig_2 */
sll $2, $2, 0x000B
mtc0 $2, $4
andi $2, $1, 0x0001 /* set sig_1 */
sll $2, $2, 0x000A
mtc0 $2, $4
break
j Start
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
L0580: nop