address.c
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/*************************************************************************
*
* File: address.c
*
* This file contains signal handlers for SIGSEGV, SIGBUS. It also
* contains routines to send and receive packets to and from the Verilog
* modules via the IPC socket connection.
*
* $Header: /root/leakn64/depot/rf/sw/n64os20l/iosim/src/address.c,v 1.2 2002/05/30 05:52:49 whs Exp $
*
*/
#include <sys/types.h>
#ifdef __sgi__
#include <sys/cachectl.h>
#include <siginfo.h>
#endif
#include <signal.h>
#include <ucontext.h>
#include <string.h>
#ifdef __sgi__
#include <bstring.h>
#endif
#include <errno.h>
#include <stdio.h>
#include <unistd.h>
#include "trace.h"
#include "sim.h"
#include "simipc.h"
#include "iomap.h"
#include "sync.h"
static void addressHandler(int, siginfo_t *, ucontext_t *);
static void killHandler(int, siginfo_t *, ucontext_t *);
static int sendReqPkt(minst_t, dir_t *, sz_t *, gregset_t);
static int isBranch(minst_t);
static int isLoadStore(minst_t, dir_t *, sz_t *);
static ulong loadStoreAddr(minst_t, gregset_t);
static void dumpData(minst_t, dir_t *, sz_t *, gregset_t);
static void dumpRegisters(siginfo_t *, gregset_t);
static void dumpLoadStoreInst(minst_t, gregset_t);
static void logTransaction(IpcPkt *);
static const struct sigaction adact = {SA_SIGINFO, addressHandler, 0};
static const struct sigaction killact = {SA_SIGINFO, killHandler, 0};
/* Extern global variable */
extern int IpcFd;
extern FILE *LogFp;
/*
* Initialize signal handlers
*/
void
ExceptionHandlerInit(void)
{
#ifdef __sgi__
sigaction(SIGKILL, &killact, NULL);
sigaction(SIGSEGV, &adact, NULL);
sigaction(SIGBUS, &adact, NULL);
#endif
} /* ExceptionHandlerInit */
/*
* Simple signal handler for SIGBUS
*/
static void
killHandler(int sig, siginfo_t *sip, ucontext_t *up)
{
#ifdef __sgi__
_TRACE(DSIGNAL, fprintf(LogFp, "**** Kill (signal=%d) ****\n", sig));
up->uc_mcontext.gregs[CTX_EPC] +=4;
#endif
} /* killHandler */
/*
* Main signal handler for SIGSEGV - this is where we decode the trapped
* instruction and send request (if valid) to Verilog for processing
*/
static void
addressHandler(int sig, siginfo_t *sip, ucontext_t *up)
{
#ifdef __sgi__
minst_t inst;
minst_t *pc;
dir_t dir;
sz_t sz;
int i, j;
unsigned int epc, cause;
unsigned int addr, rt, rs;
_TRACE(DSIGNAL, fprintf(LogFp, "**** SegV (signal=%d) ****\n", sig));
epc = up->uc_mcontext.gregs[CTX_EPC];
cause = up->uc_mcontext.gregs[CTX_CAUSE];
pc = (minst_t *)up->uc_mcontext.gregs[CTX_EPC];
_TRACE(DREGS, dumpRegisters(sip, up->uc_mcontext.gregs));
/* If we're in a branch delay slot (bit 31 of cause), print error */
if (cause & 0x80000000) {
_TRACE(DERROR, fprintf(LogFp,
"ERROR: Branch delay slot, cause=0x%08x\n", cause));
}
/* Make sure that the trapped instruction is either load/store */
inst = *pc;
if (isLoadStore(inst, &dir, &sz)) {
_TRACE(DINST, dumpLoadStoreInst(inst, up->uc_mcontext.gregs));
/* Print faulted address/data to log file */
_TRACE(DINST, dumpData(inst, &dir, &sz, up->uc_mcontext.gregs));
/* Now, send request to server for processing */
SysLockSet();
if (sendReqPkt(inst, &dir, &sz, up->uc_mcontext.gregs) > 0) {
_TRACE(DREAD|DWRITE, fprintf(LogFp,
"*** rt=0x%08x, content=0x%08x\n",
inst.i_format.rt,
up->uc_mcontext.gregs[inst.i_format.rt]));
}
SysLockReset();
}
/*
* Increment EPC by 4 so that program continues execution upon
* return from exception handler
*/
up->uc_mcontext.gregs[CTX_EPC] +=4;
if ((dir == DIR_SINGLE_LOAD) || (dir == DIR_BLOCK_LOAD)) {
_TRACE(DREGS, dumpRegisters(sip, up->uc_mcontext.gregs));
}
#endif
} /* addressHandler */
#ifdef __sgi__
/*
* Ensure that the trapped instruction is either a load/store.
* Send request (via IPC socket) to and wait for response from Verilog
* Create one IPC connection for each request.
*/
static int
sendReqPkt(minst_t inst, dir_t *dirp, sz_t *szp, gregset_t gregs)
{
unsigned address;
int i, ret, fd;
IpcPkt req, rsp;
_TRACE(DREAD|DWRITE, fprintf(LogFp,
"sendReqPkt: entering: rt=%d, gregs[rt]=0x%08x\n",
inst.i_format.rt, gregs[inst.i_format.rt]));
ret = 0;
for (i = 0; i < 3; i++) {
if ((fd = IpcOpen(IPC_CLIENT)) < 0) {
return(-1);
}
if (IpcConnect(fd) < 0) {
IpcClose(fd);
if (errno == ECONNREFUSED) {
continue; /* Try again */
}
else ret = -1;
}
else {
ret = 0;
break;
}
}
if (ret == -1) {
return(-1);
}
bzero(&req, sizeof(req));
bzero(&rsp, sizeof(rsp));
address = loadStoreAddr(inst, gregs);
/* Make sure that it's our own address */
if (IS_KSEG1(address)) {
/* Remove K1 segment */
address = K1_TO_PHYS(address);
}
else {
_TRACE(DERROR, fprintf(LogFp,
"ERROR: Invalid segment address=0x%08x\n",
address));
IpcClose(fd);
return(-1);
}
req.length = sizeof(IpcPkt);
req.code = *dirp;
req.size = *szp;
req.address = address;
req.data[0] = gregs[inst.i_format.rt];
_TRACE(DTRANS, logTransaction(&req));
if (IpcSend(fd, (char *)&req, sizeof(req)) < 0) {
IpcClose(fd);
return(-1);
}
if (IpcReceive(fd, (char *)&rsp, sizeof(rsp)) < 0) {
IpcClose(fd);
return(-1);
}
switch (rsp.code) {
case RSP_OK: ret = 0; break;
case RSP_DATA: {
if (req.code == DIR_SINGLE_LOAD) {
gregs[inst.i_format.rt] = rsp.data[0];
ret = 0;
}
else if (req.code == DIR_BLOCK_LOAD) {
gregs[inst.i_format.rt] = rsp.data[0];
ret = 0;
}
else
ret = -1;
break;
}
case RSP_ERROR: ret = -1; break;
default: ret = -1; break;
}
if (ret == -1) {
fprintf(LogFp,
"ERROR: sendReqPkt: Invalid return code=%d, request code=%d!\n",
rsp.code, req.code);
}
IpcClose(fd);
_TRACE(DREAD|DWRITE, fprintf(LogFp,
"sendReqPkt: leaving: gregs[rt]=0x%08x, rsp.code=%d\n",
gregs[inst.i_format.rt], rsp.code));
return(ret);
} /* sendReqPkt */
/*
* Return 1 if the instruction is a branch
*/
static int
isBranch(minst_t inst)
{
switch(inst.i_format.opcode) {
case beq_op: case bne_op:
case blez_op: case bgtz_op:
case beql_op: case bnel_op:
case blezl_op: case bgtzl_op:
return(1);
}
return(0);
} /* isBranch */
/*
* Ensure that the trapped instruction is either a load/store.
* If so, return the direction (LOAD/STORE) and size.
*/
static int
isLoadStore(minst_t inst, dir_t *dirp, sz_t *szp)
{
switch(inst.i_format.opcode) {
case lb_op: case lbu_op:
*dirp=DIR_SINGLE_LOAD; *szp = SIZE_1BYTE; return(1);
case lh_op: case lhu_op:
*dirp=DIR_SINGLE_LOAD; *szp = SIZE_2BYTE; return(1);
case lw_op: case lwu_op: case ll_op: case lwc1_op:
*dirp=DIR_SINGLE_LOAD; *szp = SIZE_4BYTE; return(1);
case ld_op: case lld_op: case ldc1_op:
*dirp=DIR_BLOCK_LOAD; *szp = SIZE_2WORD; return(1);
case ldl_op:
case ldr_op:
case sb_op:
*dirp=DIR_SINGLE_STORE; *szp = SIZE_1BYTE; return(1);
case sh_op:
*dirp=DIR_SINGLE_STORE; *szp = SIZE_2BYTE; return(1);
case sw_op: case sc_op: case swc1_op:
*dirp=DIR_SINGLE_STORE; *szp = SIZE_4BYTE; return(1);
case swl_op:
case swr_op:
case sd_op: case scd_op: case sdc1_op:
*dirp=DIR_BLOCK_STORE; *szp = SIZE_2WORD; return(1);
case sdl_op:
case sdr_op:
return(1);
}
return(0);
}
/*
* ldst_addr - compute data address instruction at EF_EPC would reference
* 2 versions - layered-up to allow caller to avoid
* assumptions that the outer layer makes.
*/
static ulong
loadStoreAddr(minst_t inst, gregset_t gr)
{
ulong base;
base = (inst.i_format.rs == 0) ? 0 : gr[inst.i_format.rs];
return (base + inst.i_format.simmediate);
}
/*
* Print out data related to the load/store instruction
*/
static void
dumpData(minst_t inst, dir_t *dirp, sz_t *szp, gregset_t gregs)
{
char *dirstr;
char *szstr;
unsigned int addr, data, rt, rs;
addr = loadStoreAddr(inst, gregs);
rt = inst.i_format.rt;
data = gregs[rt];
rs = inst.i_format.rs;
switch (*dirp) {
case DIR_SINGLE_LOAD: dirstr = "S-LOAD "; break;
case DIR_SINGLE_STORE: dirstr = "S-STORE"; break;
case DIR_BLOCK_LOAD: dirstr = "B-LOAD "; break;
case DIR_BLOCK_STORE: dirstr = "B-STORE"; break;
default : dirstr = "XXXXXXX"; break;
}
if ((*dirp == DIR_SINGLE_LOAD) || (*dirp == DIR_SINGLE_STORE)) {
switch (*szp) {
case SIZE_1BYTE: szstr = "1-BYTE"; break;
case SIZE_2BYTE: szstr = "2-BYTE"; break;
case SIZE_3BYTE: szstr = "3-BYTE"; break;
case SIZE_4BYTE: szstr = "4-BYTE"; break;
default : szstr = "XXXXXX"; break;
}
}
if ((*dirp == DIR_BLOCK_LOAD) || (*dirp == DIR_BLOCK_STORE)) {
switch (*szp) {
case SIZE_2WORD: szstr = "2-WORD"; break;
case SIZE_4WORD: szstr = "4-WORD"; break;
case SIZE_8WORD: szstr = "8-WORD"; break;
default : szstr = "XXXXXX"; break;
}
}
/* Print faulted address/data to standard out */
fprintf(LogFp,
"* Inst=0x%08x: %s %s addr=0x%08x data=0x%08x\n",
inst, dirstr, szstr, addr, data);
fprintf(LogFp,
"\t\t(rs=%d, val=0x%08x) (rt=%d, val=0x%08x) ofs=0x%08x\n\n",
rs, gregs[rs], rt, gregs[rt], inst.i_format.simmediate);
} /* dumpData */
/*
* Print out all register contents
*/
static void
dumpRegisters(siginfo_t *sip, gregset_t gregs)
{
int i, j;
fprintf(LogFp, "Fault: address=0x%08x, code=%d\n",
sip->si_addr, sip->si_code);
fprintf(LogFp, "EPC=0x%08x\tInstr=0x%08x\n",
gregs[CTX_EPC], *(unsigned int *)gregs[CTX_EPC]);
for (i = 0; i < (NGREG/4); i++) {
for (j = 0; j < 4; j++) {
fprintf(LogFp, "[%2d]=0x%08x ",
(i*4)+j, gregs[(i*4)+j]);
}
fprintf(LogFp, "\n");
}
} /* dumpRegisters */
/*
* Print out summarized info related to the load/store instruction
*/
static void
dumpLoadStoreInst(minst_t inst, gregset_t gregs)
{
fprintf(LogFp, "Instr=0x%08x is load/store\n", inst);
fprintf(LogFp, "opcode=0x%08x\n", inst.i_format.opcode);
fprintf(LogFp, "rs=0x%08x, content=0x%08x\n",
inst.i_format.rs, gregs[inst.i_format.rs]);
fprintf(LogFp, "rt=0x%08x, content=0x%08x\n",
inst.i_format.rt, gregs[inst.i_format.rt]);
fprintf(LogFp, "address=0x%08x\n",
loadStoreAddr(inst, gregs));
} /* dumpLoadStoreInst */
/*
* Print out IO transaction
*/
static void
logTransaction(IpcPkt *req)
{
switch (req->code) {
case REQ_BLOCK_READ:
case REQ_SINGLE_READ: {
fprintf(LogFp, "RD -> : A=0x%08x\n", req->address);
break;
}
case REQ_BLOCK_WRITE:
case REQ_SINGLE_WRITE: {
fprintf(LogFp, "WR <- : A=0x%08x, D=0x%08x\n",
req->address, req->data[0]);
break;
}
}
} /* logTransaction */
#endif