/*************************************************************************
 *
 *  File: randtest.c
 *
 *  This file contains the main routine for the I/O random test.
 *
 *  $Header: /root/leakn64/depot/rf/sw/n64os20l/iosim/src/randtest.c,v 1.2 2002/05/30 05:52:50 whs Exp $
 *
 */

#include <sys/types.h>		
#ifdef __sgi__
	#include <sys/cachectl.h>
	#include <sys/sysmp.h>
#endif
#include <sys/mman.h>
#include <ctype.h>
#include <errno.h>
#include <limits.h>
#include <fcntl.h>
#include <getopt.h>
#ifdef __sgi__
	#include <libelf.h>
#endif
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <unistd.h>

#include <sys/time.h>		/* Needed for select */
#include <math.h>		/* Needed for random */
#include <sys/prctl.h>		/* Needed for sproc */
#include <signal.h>		/* Needed for signal */
#ifdef __sgi__
	#include <task.h>
#endif

#include "trace.h"
#include "sim.h"
#include "simipc.h"
#include "iomap.h"
#include "iotest.h"
#include "sync.h"
#include "verify.h"


/***************************************************************************
 * Definitions
 */
#define	DEFAULT_LOOP_COUNT	500
#define	DEFAULT_RUN_COUNT	1	/* Minimum run count for each thread */
#define	DEFAULT_TEST_SEED	1
#define	DEFAULT_FREQ_SEED	1

/*
 * DP List ring buffer size (in number of 32-bit words)
 */
#define	DPL_RING_SIZE	124	/* 124 32-bit words == 62 64-bit longs */

#define FROM_RDRAM	0
#define FROM_DMEM1	1
#define FROM_DMEM2	2
#define MAX_RINGBUFFERS	3

/*
 * Default address ranges for testing
 *
			RDRAM
	      0 +---------------------+		04000000 +----------------+
		|                     |			 |     DMEM       |
		|                     |			 |                |
		|                     |			 |                |
		|                     |			 +----------------+
		|                     |		         |   128 Bytes    |
       01e7000  +---------------------+         04000fff +----------------+
		|      MI (10 KB)     |         04001000 |     IMEM       |
		+---------------------+                  |                |
		|      PI             |                  |                |
		+---------------------+                  +----------------+
		|      SI             |                  |   128 Bytes    |
		+---------------------+         04001fff +----------------+
		|      AI             |
		+---------------------+
		|      SP             |
		+---------------------+
		|                     |
       01fffff  +---------------------+
 */
#define	RDRAM_RAND_BASE		(RDRAM_0_END+1-(60*1024)) /* 100 KB from end */
#define RDRAM_TEST_SIZE		(3*1024)		   /* 3 KB each */

#define	RDRAM_VI_START		(RDRAM_RAND_BASE)
#define	RDRAM_VI_END		(RDRAM_VI_START+(30*1024)-1)

#define	RDRAM_MI_START		(RDRAM_VI_END+1)
#define	RDRAM_MI_END		(RDRAM_MI_START+RDRAM_TEST_SIZE-1)

#define	RDRAM_PI_START		(RDRAM_MI_END+1)
#define	RDRAM_PI_END		(RDRAM_PI_START+RDRAM_TEST_SIZE-1)

#define	RDRAM_SI_START		(RDRAM_PI_END+1)
#define	RDRAM_SI_END		(RDRAM_SI_START+RDRAM_TEST_SIZE-1)

#define	RDRAM_AI_START		(RDRAM_SI_END+1)
#define	RDRAM_AI_END		(RDRAM_AI_START+RDRAM_TEST_SIZE-1)

#define	RDRAM_SP_START		(RDRAM_AI_END+1)
#define	RDRAM_SP_END		(RDRAM_SP_START+RDRAM_TEST_SIZE-1)

#define	RDRAM_DP_START		((RDRAM_SP_END+1) + 0x3e0) /* +992 */
#define	RDRAM_DP_END		(RDRAM_DP_START+RDRAM_TEST_SIZE-1)

#define	DP_DMEM_TEST_SIZE	(DPL_RING_SIZE*4)  /* 62 64-bit words */
#define DMEM_TEST_SIZE		(128)		   /* 128 bytes */
#define IMEM_TEST_SIZE		(128)		   /* 128 bytes */

#define	DMEM_START		(SP_DMEM_END+1-128)
#define	DMEM_END		(DMEM_START+DMEM_TEST_SIZE-1)

#define	DP_DMEM_START	(SP_DMEM_END+1-(DMEM_TEST_SIZE+DP_DMEM_TEST_SIZE))
#define	DP_DMEM_END		(DP_DMEM_START+DP_DMEM_TEST_SIZE-1)
#define	DP2_DMEM_START		0x04000800	/* Evan's ring buffer */
#define	DP2_DMEM_END		0x040008FF

#define	IMEM_START		(SP_IMEM_END+1-128)
#define	IMEM_END		(IMEM_START+IMEM_TEST_SIZE-1)

#define	PI_ROM1_START		0x08000000	/* 4 MB each */
#define	PI_ROM1_END		0x08400000

#define	PI_ROM2_START		0x10000000	/* 4 MB each */
#define	PI_ROM2_END		0x10400000

#define	PI_WROM_START1		0x09000000	/* 2 MB each */
#define	PI_WROM_END1		0x09200000
#define	PI_WROM_START2		0x09200000	/* 2 MB each */
#define	PI_WROM_END2		0x09400000

#define	SI_ROM_START		0x1fc00000	/* 1984 bytes (4-byte status) */
#define	SI_ROM_END		0x1fc007bc

#define	SI_RAM_START		0x1fc007c0	/* 64 bytes */
#define	SI_RAM_END		0x1fc007ff

#define RDRAM_IMEM_TEST_ID	0x00137000

/*
 * IO/DMA states
 */
#define	IO_STATE_INIT 		1	/* One-time-only init steps */
#define	IO_STATE_START		2	/* Start IO transaction */
#define	IO_STATE_CHECK_STATUS	3	/* Check for IO (i.e. DMA) completion */
#define	IO_STATE_COMPARE	4	/* Compare data */

/*
 * Extra IO/DMA states for doing multi-frame video tests
 */

#define IO_STATE_CHECK_F0_LAN1  6
#define IO_STATE_CHECK_MID_LAN1 7
#define IO_STATE_CHECK_F1_LAN1  8
#define IO_STATE_CHECK_END_LAN1 9

#define IO_STATE_CHECK_F0_LAN2  10
#define IO_STATE_CHECK_MID_LAN2 11
#define IO_STATE_CHECK_F1_LAN2  12
#define IO_STATE_CHECK_END_LAN2 13

#define IO_STATE_CHECK_F0_LPN1  14
#define IO_STATE_CHECK_MID_LPN1 15
#define IO_STATE_CHECK_F1_LPN1  16
#define IO_STATE_CHECK_END_LPN1 17

#define IO_STATE_CHECK_F0_HAN1  18
#define IO_STATE_CHECK_MID_HAN1 19
#define IO_STATE_CHECK_F1_HAN1  20
#define IO_STATE_CHECK_END_HAN1 21

#define IO_STATE_CHECK_F0_HPF2  22
#define IO_STATE_CHECK_MID_HPF2 23
#define IO_STATE_CHECK_F1_HPF2  24
#define IO_STATE_CHECK_END_HPF2 25


/*
 * Messages
 */
 /* test id, description, expected val, actual val, passed/failed */
#define RTST_MSG_RES_STR "Test %3d (%15s: %08x %08x %08x %08x)\n"
#define RTST_MSG_RES2_STR "Test %3d (%15s: %08x %08x %08x %08x) -> %s\n"
#define RTST_ERROR_STR "\t****ERROR: src=%08x:%08x, dst=%08x:%08x\t\t -> %s\n"

#define THREAD_PRINT_MSG	\
    "T: id=%2d, pid=%4d, entry=0x%08x, R=%3d, B=%1d, S=%1d, I=%1d, name=%s\n"

#define	BUSY_STR	"Busy"
#define	DONE_STR	"Done"

/*
 * Macros
 */
#define INSERT_RESULT(ret)	(ret == -1 ? FAIL_STR : PASS_STR)

#define PRINT_RESULT(ret)	{				\
	if (ret == -1) fprintf(LogFp, "-> %s\n", FAIL_STR);	\
	else fprintf(LogFp, "-> %s\n", PASS_STR); }		\

#define RANDLOG_ERROR(src,w1,dst,w2) 				\
		fprintf(LogFp, RTST_ERROR_STR, src, w1, dst, w2, FAIL_STR)

/***************************************************************************
 * External variables
 */
extern unsigned long	Dflags;
extern FILE		*LogFp, *CmdFp;
extern char		*LogFile;


/***************************************************************************
 * Data structures
 */
typedef struct _ThreadCmd {
	int	pid;				/* Thread process id */
	void	(*entry)(struct _ThreadCmd *);	/* Thread entry point */
	int	runCount;			/* Total number of run
							(Parent) */
	int	busy;				/* Busy running (Child)  */
	int	state;				/* IO internal state */
	int	inProgress;			/* IO transaction is still
						   	in progress */
	char	*name;
} ThreadCmd;

typedef	void	(*SPROC_T)(void *);


/***************************************************************************
 * Global variables
 */
/* How many times we need to run */
unsigned int LoopCount	= DEFAULT_LOOP_COUNT;
unsigned int MinRunCount= DEFAULT_RUN_COUNT;

/* Random seed for selecting a test */
unsigned int TestSeed	= DEFAULT_TEST_SEED;

/* Random seed for frequency of run for a test */
unsigned int FreqSeed	= DEFAULT_FREQ_SEED;

/* Size of memory reserved for each IO subsystem for testing */
unsigned int RdramTestSize	= RDRAM_TEST_SIZE;

/* Define RDRAM address range for MI testing */
unsigned int MiRdramStart	= RDRAM_MI_START;
unsigned int MiRdramEnd		= RDRAM_MI_END;

/* Define RDRAM address range for PI testing */
unsigned int PiRdramStart	= RDRAM_PI_START;
unsigned int PiRdramEnd		= RDRAM_PI_END;
unsigned int PiRomStart[2]	= {{PI_ROM1_START}, {PI_ROM2_START}};
unsigned int PiRomEnd[2]	= {{PI_ROM1_END}, {PI_ROM2_END}};
unsigned int PiWRomStart1	= PI_WROM_START1;
unsigned int PiWRomEnd1		= PI_WROM_END1;
unsigned int PiWRomStart2	= PI_WROM_START2;
unsigned int PiWRomEnd2		= PI_WROM_END2;

/* Define RDRAM address range for SI testing */
unsigned int SiRdramStart	= RDRAM_SI_START;
unsigned int SiRdramEnd		= RDRAM_SI_END;
unsigned int SiRomStart		= SI_ROM_START;
unsigned int SiRomEnd		= SI_ROM_END;
unsigned int SiRamStart		= SI_RAM_START;
unsigned int SiRamEnd		= SI_RAM_END;

/* Define RDRAM address range for AI testing */
unsigned int AiRdramStart	= RDRAM_AI_START;
unsigned int AiRdramEnd		= RDRAM_AI_END;

/* Define RDRAM address range for SP testing */
unsigned int SpRdramStart	= RDRAM_SP_START;
unsigned int SpRdramEnd		= RDRAM_SP_END;
unsigned int SpImemStart	= IMEM_START;
unsigned int SpImemEnd		= IMEM_END;
unsigned int SpDmemStart	= DMEM_START;
unsigned int SpDmemEnd		= DMEM_END;

/* Define RDRAM address range for DP testing */
unsigned int DpRdramStart	= RDRAM_DP_START;
unsigned int DpRdramEnd		= RDRAM_DP_END;
unsigned int DpDmemStart	= DP_DMEM_START;
unsigned int DpDmemEnd		= DP_DMEM_END;
unsigned int Dp2DmemStart	= DP2_DMEM_START;
unsigned int Dp2DmemEnd		= DP2_DMEM_END;

/* Define RDRAM address range for VI testing */
unsigned int ViRdramStart	= RDRAM_VI_START;
unsigned int ViRdramEnd		= RDRAM_VI_END;

/* To turn on 2nd RDRAM */
unsigned int Rdram1Enabled	= 1;

/* RDRAM size: 4 MB, 6MB, or 8MB 
 *	1) 4 MB = 2 * 2MB
 *	2) 6 MB = 2MB + (2 * 1MB) + 2MB
 *	3) 8 MB = 4 * 2MB
 */
unsigned int RdramSize		= 4;	/* Use 4MB for default */

/* To kill the iorand environment - can be set in any test */
unsigned int QuickDeath		= 0;

/* To enable DMA compare and disable round-robin scheduing */
unsigned int CompareEnabled	= 1;
unsigned int RoundRobinEnabled	= 0;

/* Flag to tell if IMEM dma80 test is enabled or not */
unsigned int dma80Enabled	= 1;

/* Flag to tell if AI is running at 44.1 KHz */
unsigned int Ai441Enabled	= 0;

/* Only for standalone */
#ifdef STANDALONE
int	errorTotal = 0;
int	errorCount = 0;
#endif

/* Round robin randomizing array */
int *ProcessOrder;

/***************************************************************************
 * Static declarations
 */
unsigned int spLocDmaActive	= 0;
unsigned int dpcRandDmaActive	= 0;

/* Display list parameters */
unsigned int dplStartAddr	= 0;
unsigned int dplEndAddr		= 0;
unsigned int dplCurrAddr	= 0;

/* Display list ring buffer parameters */
unsigned int dplRingSize	= 0;
unsigned int dplRingSource	= 0;
unsigned int dplRingStartp	= 0;
unsigned int dplRingEndp	= 0;


/***************************************************************************
 * Extern declarations
 */


/***************************************************************************
 * Forward declarations
 */
static void setupRingBuffer(void);

void	KillAllThreads(void);
int	CheckInterrupt(unsigned int, unsigned int *);
void	FlushVerifyInfo(void);
void	PrintActiveTable(void);
int	MemSmplCompare(int , int , int , int );
void	rangeExpand(char *);
void    initRoundRobin(void);

ThreadCmd * findActiveThread(void *entry);

void	MiRandIoRd(ThreadCmd *);
void	MiRandIoWrRd(ThreadCmd *);

void	PiRandIoRd(ThreadCmd *);
void	PiRandIoWrRd(ThreadCmd *);
void	PiRandDma(ThreadCmd *);

void	SiRandIoRd(ThreadCmd *);
void	SiRandIoWrRd(ThreadCmd *);
void	SiRandDma(ThreadCmd *);

void	AiRandDma(ThreadCmd *);

void	ViRandDma(ThreadCmd *);
void	ViMLF2Dma(ThreadCmd *);
void    ViBigDma(ThreadCmd *);
void    ViLan2Dma(ThreadCmd *);

void	SpRandIoRd(ThreadCmd *);
void	SpRandIoWrRd(ThreadCmd *);
void	SpRandDma(ThreadCmd *);
void	SpLocDma(ThreadCmd *);

void	DpcRandDma(ThreadCmd *);

/* New test procedures for vi, added by kluster */

void    ViMLN1Dma(ThreadCmd *);
void    ViMLN2Dma(ThreadCmd *);
void    ViMLP1Dma(ThreadCmd *);
void    ViMHN1Dma(ThreadCmd *);
void    ViMHF2Dma(ThreadCmd *);

void    ViDTH2Dma(ThreadCmd *);
   
void	SpDummyDma(ThreadCmd *);

/*
 * IDs for different test threads
 */
#define MI_RAND_BASE		0
#define MI_IOR_ID		(MI_RAND_BASE+0)
#define MI_IOWR_ID		(MI_RAND_BASE+1)

#define PI_RAND_BASE		(MI_IOWR_ID+1)
#define PI_IOR_ID		(PI_RAND_BASE+0)
#define PI_IOWR_ID		(PI_RAND_BASE+1)
#define PI_DMA_ID		(PI_RAND_BASE+2)

#define SI_RAND_BASE		(PI_DMA_ID+1)
#define SI_IOR_ID		(SI_RAND_BASE+0)
#define SI_IOWR_ID		(SI_RAND_BASE+1)
#define SI_DMA_ID		(SI_RAND_BASE+2)

#define AI_RAND_BASE		(SI_DMA_ID+1)
#define AI_DMA_ID		(AI_RAND_BASE+0)

#define VI_RAND_BASE		(AI_DMA_ID+1)
#define VI_DMA_ID		(VI_RAND_BASE+0)

#define SP_RAND_BASE		(VI_DMA_ID+1)
#define SP_IOR_ID		(SP_RAND_BASE+0)
#define SP_IOWR_ID		(SP_RAND_BASE+1)
#define SP_DMA_ID		(SP_RAND_BASE+2)
#define SP_LOC_ID		(SP_RAND_BASE+3)

#define DPC_RAND_BASE		(SP_LOC_ID+1)
#define DPC_DMA_ID		(DPC_RAND_BASE+0)

/***************************************************************************
 * Test Thread Table
 */
ThreadCmd RandThreadTable[] = {
 /*
  *   ID	PID	Entry		R  B  S  I	EntryName
  * ====================================================================
  */
  { /*  0 */   	 0,	MiRandIoRd,	0, 0, 1, 0,	"MiRandIoRd"	},
  { /*  1 */     0,	MiRandIoWrRd,	0, 0, 1, 0,	"MiRandIoWrRd"},

  { /*  2 */     0,	PiRandIoRd,	0, 0, 1, 0,	"PiRandIoRd"	},
  { /*  3 */     0,	PiRandIoWrRd,	0, 0, 1, 0,	"PiRandIoWrRd"},
  { /*  4 */     0,	PiRandDma,	0, 0, 1, 0,	"PiRandDma"	},

  { /*  5 */     0,	SiRandIoRd,	0, 0, 1, 0,	"SiRandIoRd"	},
  { /*  6 */     0,	SiRandIoWrRd,	0, 0, 1, 0,	"SiRandIoWrRd"},
  { /*  7 */     0,	SiRandDma,	0, 0, 1, 0,	"SiRandDma"	},

  { /*  8 */     0,	AiRandDma,	0, 0, 1, 0,	"AiRandDma"	},

  { /*  9 */     0,	ViMLF2Dma,	0, 0, 1, 0,	"ViMLF2Dma"	},

  { /* 10 */     0,	SpRandIoRd,	0, 0, 1, 0,	"SpRandIoRd"	},
  { /* 11 */     0,	SpRandIoWrRd,	0, 0, 1, 0,	"SpRandIoWrRd"},
  { /* 12 */     0,	SpRandDma,	0, 0, 1, 0,	"SpRandDma"	},
  { /* 13 */     0,	SpLocDma,	0, 0, 1, 0,	"SpLocDma"	},

  { /* 14 */     0,	DpcRandDma,	0, 0, 1, 0,	"DpcRandDma"	},

  /* New tests for vi testing */

  { /* 15 */     0,	SpDummyDma,	0, 0, 1, 0,	"SpDummyDma"	},
  { /* 16 */     0,     ViMLN1Dma,      0, 0, 1, 0,     "ViMLN1Dma"     },
  { /* 17 */     0,     ViMLN2Dma,      0, 0, 1, 0,     "ViMLN2Dma"     },
  { /* 18 */     0,     ViMLP1Dma,      0, 0, 1, 0,     "ViMLP1Dma"     },
  { /* 19 */     0,     ViMHN1Dma,      0, 0, 1, 0,     "ViMHN1Dma"     },
  { /* 20 */     0,     ViMHF2Dma,      0, 0, 1, 0,     "ViMHF2Dma"     },

  /* Dither vi test */
  { /* 21 */     0,     ViDTH2Dma,      0, 0, 1, 0,     "ViDTH2Dma"     },

};

int RandTableSize = sizeof(RandThreadTable)/sizeof(RandThreadTable[0]);

ThreadCmd **ActiveThreadTable;

int ActiveTableSize;


/***************************************************************************
 * Main random IO test loop
 *
 * The idea is to have a table containing of various test routines that can
 * be spawned off as a thread (via sproc). The parent scheduler randomly 
 * selects (based on UNIX random() function) which test thread to run. 
 * Each thread contains a main loop where it processes the IO transaction and
 * then blocks itself, waiting to be unblocked by the parent scheduler upon the
 * next invocation. The thread exits only when it receives a SIGINT signal from
 * the parent; this occurs at the end of the all testing. Parent and child 
 * communicate over global data structures. Once started, the child thread
 * sets a busy flag, telling the parent to not invoke this thread again. And 
 * once the child finishes its task, it resets the busy flag and blocks itself. 
 * Based on the random number generated, the parent will most likely select this 
 * thread again, especially when the busy flag is cleared. 
 * 
 * In general, there 3 types of test thread: one to perform only IO read-compare
 * from a memory address range that has been initialized with pattern data, 
 * one to perform IO write-read-compare, and one to perform DMA transaction 
 * between an IO subsytem and RDRAM. The DMA thread needs to have its own 
 * internal state machine to minimize the time it spends hogging CPU and
 * RCP. For example, in state 1, the thread will start a DMA transaction, 
 * records the transaction and returns. In its next invocation, it will enter 
 * state 2 where it checks for DMA completion and returns. The thread will
 * stay in state 2 (after numerous invocation) until the DMA busy bit is off.
 * Once the busy bit is off, the next invocation will put the thread into
 * its last state 3 to compare the data for correctness. Once again, the thread
 * need to distribute its time spent in this state over numerous invocations.
 *
 * Ideally, there should be 2 random seeds: one for selecting a test to run, and
 * the other for choosing the number of times (or frequency) that this test
 * should run. For simplicity, we'll simply use 1 seed to generate random 
 * numbers which only the low 8 bits are used.
 */
int
IoRandTest(char *testRange) 
{

	int 		i, j, ret;
	int 		status, done;
	int 		randomNeeded, stillRunning;
	unsigned int	count;
	unsigned int	testRand  = 0;
	ThreadCmd	*thread;
	struct timeval 	timeout;


	_TRACE(DLOG, printf("IoRandTest: entered\n"));

	rangeExpand(testRange);

	_TRACE(DLOG, printf("RandTableSize = %d\n", RandTableSize));
	_TRACE(DLOG, printf("ActiveTableSize = %d\n", ActiveTableSize));

	/*
	 * Initialize random seeds 
	 */
	ret =srandom(TestSeed);

	initRoundRobin();
	
	randomNeeded = 1;
	done  = 0;
	count = 1;
	while (!done && !QuickDeath) {
		/* 
		 * First, get the random number to select which thread to run 
		 */
		if (randomNeeded) {
			if (RoundRobinEnabled)
				testRand = (testRand+1) % ActiveTableSize;
			else
				testRand = random() % ActiveTableSize;
		}
		else {
		/*
		 * Here, we have finished the testing but there are still
		 * transactions in progress (most likely DMAs). So, we need
		 * to keep activate the in-progress thread to run until 
		 * it's finished. We sequentially search the table for each
		 * unfinished thread and sticks with it.
		 */
			for (i=0; i < ActiveTableSize; i++) {
				if (ActiveThreadTable[i]->inProgress == 1) {
					testRand = i;
					break;
				}  /* if */
			}  /* for */
		}  /* if */

		thread = ActiveThreadTable[ProcessOrder[testRand]];

		_TRACE(DLOG, printf(
			"Count #%4d: thread id=%2d, name=%s\n", 
			count, testRand, thread->name));

		thread->entry(thread);
		thread->runCount++;

		_TRACE(DLOG, printf(THREAD_PRINT_MSG,
			thread - RandThreadTable,
			thread->pid, thread->entry,
			thread->runCount, thread->busy,
			thread->state, thread->inProgress, 
			thread->name));
		count++;

		/* 
		 * Check to see if we're done: 
		 *	1) LoopCount is reached
		 *	2) Every thread has been run at least MinRunCount
		 *	3) No outstanding DMA test
		 */
		if (count > LoopCount) {
			stillRunning = 0;
			for (i=0; i < ActiveTableSize; i++) {
				if (ActiveThreadTable[i]->runCount <
				    MinRunCount) 
					break;
				if (ActiveThreadTable[i]->inProgress == 1) 
					stillRunning = 1;
			}  /* for */
			if (i >= ActiveTableSize) {
				if (stillRunning)
					randomNeeded = 0;
				else 
					done = 1;
			}  /* if */
		}  /* if */

	}  /* while */

	PrintActiveTable();

	return(0);

}  /* IoRandTest */


/***************************************************************************
 * Thread entry routines
 */
void
MiRandIoRd(ThreadCmd *thread)
{
	unsigned int	data;
	int		ret;
	static unsigned int address = 0;

	/* Assume that RDRAM has been initialized with data = address */
	if ((address == 0) || 
		(address > (MiRdramStart+(RdramTestSize/2))))
		address = MiRdramStart - 4;
	address = (address + 4) & 0xfffffffc;
	ret = MemReadCompare(address, address, 0, 0);
	fprintf(LogFp, RTST_MSG_RES2_STR,
		thread - RandThreadTable, thread->name,
		address, address, 0, 0,
		INSERT_RESULT(ret));

}  /* MiRandIoRd */


void
MiRandIoWrRd(ThreadCmd *thread)
{
	int		ret = 0;
	static unsigned int address = 0;
	static unsigned int maxAddress = 0;

	/* If 2nd RDRAM is enabled, we use this thread to test it */
#if 0
	if (Rdram1Enabled) {
		if ((address == 0) || 
			(address > (RDRAM_1_START+0x80000+RdramTestSize)))
			address = RDRAM_1_START+0x80000 - 4;
	}
#endif
	if ((address == 0) || (address > MiRdramEnd))
		address = MiRdramStart+(RdramTestSize/2) - 4; 

	address = (address + 4) & 0xfffffffc;

	ret = MemWriteRead(address, address, address, 0);
	fprintf(LogFp, RTST_MSG_RES2_STR,
		thread - RandThreadTable, thread->name,
		address, address, 0, 0,
		INSERT_RESULT(ret));

}  /* MiRandIoWrRd */


/***************************************************************************
 * PI thread routines
 */
void
PiRandIoRd(ThreadCmd *thread)
{
	unsigned int		data, stat;
	static unsigned int	rom 	= 1;
	static unsigned int	address = 0; 

	/* 
 	 * For PI, we need to check for both DMA/IO busy bits before 
	 * perform IO read/write - If they're busy, we simply exit and 
	 * try again later
 	 */
	/* Assume that ROM 1 & 2 have been initialized with 
	 * data = address 
	 */
	if ((address == 0) || (address > (PiRomStart[rom]+100))) {
		rom = 1 - rom;
		address = PiRomStart[rom] - 4;
	}
	address = (address + 4) & 0xfffffffc;

#ifdef __sgi__	/* K1--BUG */
        stat = *(vu_int *)PHYS_TO_K1(PI_STATUS_REG);  
#else
        stat = (vu_int) (IO_READ(PI_STATUS_REG)); 
#endif
	if (!(stat & (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY))) {

		/*
		data = PiTestIoRead(address, address, 0, 0);
		*/
#ifdef __sgi__  /* K1--BUG */
		data = *(vu_int *)PHYS_TO_K1(address);
#else 
                data = (vu_int)(IO_READ(address)); 
#endif
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, data, 0, stat, DONE_STR);
	}
	else {
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, 0, 0, stat, BUSY_STR);
	}

}  /* PiRandIoRd */


void
PiRandIoWrRd(ThreadCmd *thread)
{
	int			ret;
	unsigned int		stat;
	static unsigned int	address = 0;

	/* 
	 * For PI, we need to check for both DMA/IO busy bits before 
	 * perform IO read/write - If they're busy, we simply exit and 
	 * try again later
	 */
	if ((address == 0) || (address > PiWRomEnd1))
		address = PiWRomStart1 - 4;
	address = (address + 4) & 0xfffffffc;
	
#ifdef __sgi__    /* K1--BUG */
	stat = *(vu_int *)PHYS_TO_K1(PI_STATUS_REG); 
#else
        stat = (vu_int)(IO_READ(PI_STATUS_REG)); 
#endif
	if (!(stat & (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY))) {

		ret = PiTestIoWrite(address, address, 0, 0);
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, address, 0, stat, INSERT_RESULT(ret));
	}
	else {
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, address, 0, stat, BUSY_STR); 
	}

}  /* PiRandIoWrRd */


void
PiRandDma(ThreadCmd *thread)
{
	int			ret;
	unsigned int		stat;
	static	unsigned int	dir     = DIR_FROM_RAM;
	static	unsigned int	piAddr  = 0;
	static	unsigned int	ramAddr = 0;
	static	unsigned int	nbytes	= 0; 
	static	unsigned int	lastStat= 0; 
	static unsigned int	rom 	= 1;

	switch (thread->state) {
		case IO_STATE_INIT:
		case IO_STATE_START: {
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(PI_STATUS_REG);
#else 
			stat = (vu_int)(IO_READ(PI_STATUS_REG));
#endif 
			if (!(stat & 
				(PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY))) {

			    thread->inProgress = 1;
			    /* Toggle direction */
			    dir = (dir==DIR_FROM_RAM) ? DIR_TO_RAM:DIR_FROM_RAM;

			    /* If DMA to RDRAM, then we use the 2 ROM models
	 		     */
			    if (dir == DIR_TO_RAM) {
				rom = 1 - rom;
				piAddr = PiRomStart[rom];
			    }
			    else {	/* we use the WROM model */
				piAddr = PiWRomStart2;
			    }

			    /* 
			     * We randomly pick nbytes to be between 
			     * 128 and 2044 (0x7fc) bytes 
			     */
			    nbytes = (128 + random()) & 0x7fc;

			    /* Set RDRAM address */
			    if ((ramAddr == 0) || 
			    	(ramAddr > (PiRdramEnd - (nbytes+4))))
				ramAddr = PiRdramStart - 128;
			    ramAddr += 128;

			    ret = PiTestDma(dir, piAddr, ramAddr, nbytes);
			    fprintf(LogFp, RTST_MSG_RES2_STR,
			    	thread - RandThreadTable, "PiTestDma",
			    	dir, piAddr, ramAddr, nbytes,
			    	INSERT_RESULT(ret));
			    thread->state = IO_STATE_CHECK_STATUS;
			} else {
			    fprintf(LogFp, RTST_MSG_RES2_STR,
			    	thread - RandThreadTable, "PiTestDma",
			    	dir, piAddr, ramAddr, stat, BUSY_STR); 
			}
			break;
		}
		case IO_STATE_CHECK_STATUS: {
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(PI_STATUS_REG);
#else
			stat = (vu_int)(IO_READ(PI_STATUS_REG));
#endif
			if (stat != lastStat)
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "PiDmaStatus", 
					PI_STATUS_REG, PI_STATUS_DMA_BUSY, 
					1, stat, DONE_STR);
			lastStat = stat;
			if (!(stat & PI_STATUS_DMA_BUSY)) {
				if (CheckInterrupt(MI_INTR_PI, &stat)) {
#ifdef __sgi__  /* K1--BUG */
					*(vu_int *)PHYS_TO_K1(PI_STATUS_REG) =
						PI_CLR_INTR;
#else 
					IO_WRITE(PI_STATUS_REG, PI_CLR_INTR);
#endif
					fprintf(LogFp, RTST_MSG_RES2_STR,
						thread - RandThreadTable,
						"PiCheckIntr", 
						MI_INTR_REG, MI_INTR_PI, 
						0, stat, PASS_STR);
				}
				else {
					fprintf(LogFp, RTST_MSG_RES2_STR,
						thread - RandThreadTable,
						"PiCheckIntr", 
						MI_INTR_REG, MI_INTR_PI, 
						0, stat, FAIL_STR);
        				errorTotal++;
				}
				if (CompareEnabled)
					thread->state = IO_STATE_COMPARE;
				else {
					thread->state = IO_STATE_START;
					thread->inProgress = 0;
				}
			}
			break;
		}
		case IO_STATE_COMPARE: {
			/* Here we compare the 1st word, last word */
			ret = MemSmplCompare(piAddr, ramAddr, nbytes/4, 0);
			fprintf(LogFp, RTST_MSG_RES2_STR,
				thread - RandThreadTable,
				"PiDmaCompare",
				piAddr, 
				ramAddr, nbytes/4, 0, INSERT_RESULT(ret));
			thread->state = IO_STATE_START;
			thread->inProgress = 0;
			break;
		}
		default: {
                        _TRACE(DERROR,
                        fprintf(LogFp,
                                "\tERROR: Illegal IO state encountered!\n"));
		}
	}  /* switch */

}  /* PiRandDma */


/***************************************************************************
 * SI thread routines
 */
void
SiRandIoRd(ThreadCmd *thread)
{
	int			ret;
	unsigned int		data, stat;
	static unsigned int 	address = 0;

	/* Assume that ROM has been initialized with data = address */
	if ((address == 0) || (address > SiRomEnd)) {
		address = SiRomStart - 4;
	}
	address = (address + 4) & 0xfffffffc;
	data    = (address >> 2) & 0x0000ffff;
#ifdef __sgi__  /* K1--BUG */
	stat = *(vu_int *)PHYS_TO_K1(SI_STATUS_REG);
#else
	stat = (vu_int)(IO_READ(SI_STATUS_REG));
#endif 
	if (!(stat & (SI_STATUS_DMA_BUSY | SI_STATUS_RD_BUSY)) &&
		(RandThreadTable[SI_DMA_ID].inProgress == 0)) {
		ret = SiTestIoRead(address, data, 0, 0);
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, data, 0, stat, INSERT_RESULT(ret));
	}
	else {
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, data, 0, stat, BUSY_STR);
	}

}  /* SiRandIoRd */


void
SiRandIoWrRd(ThreadCmd *thread)
{
	int			ret;
	unsigned int		stat;
	static unsigned int	address = 0;

	/* 
	 * For SI, we need to check for both DMA/IO busy bits before 
	 * perform IO write - If they're busy, we simply exit and try 
	 * again later
	 */
	if ((address == 0) || (address > SiRamEnd))
		address = SiRamStart - 4;
	address = (address + 4) & 0xfffffffc;

#ifdef __sgi__  /* K1--BUG */
	stat = *(vu_int *)PHYS_TO_K1(SI_STATUS_REG);
#else
	stat = (vu_int)(IO_READ(SI_STATUS_REG));
#endif
		
	/*
	 * Need to check for busy bits AND no outstanding DMA
	 * in progress; otherwise, this routine will overwrite
	 * one 32-bit word in the 64 bytes SI RAM and cause DMA
	 * compare to fail.
	 */
	if (!(stat & (SI_STATUS_DMA_BUSY | SI_STATUS_RD_BUSY)) &&
		(RandThreadTable[SI_DMA_ID].inProgress == 0)) {
		ret = SiTestIoWrite(address, address, 0, 0);
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, address, 0, stat, INSERT_RESULT(ret));
	}
	else {
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, address, 0, stat, BUSY_STR);
	}

}  /* SiRandIoWrRd */


void
SiRandDma(ThreadCmd *thread)
{
	int			ret;
	unsigned int		stat;
	static	unsigned int	type    = SI_WR64B;
	static	unsigned int	siAddr  = 0;
	static	unsigned int	ramAddr = 0;
	static	unsigned int	nbytes	= 64;
	static	unsigned int	lastStat= 0;

	switch (thread->state) {
		case IO_STATE_INIT:
		case IO_STATE_START: {
			thread->inProgress = 1;
			type = (type==SI_RD64B) ? SI_WR64B : SI_RD64B;
			if ((ramAddr == 0) || 
			    (ramAddr > (SiRdramEnd - (nbytes+4))))
				ramAddr = SiRdramStart - 8;
			ramAddr += 8;
			siAddr = SiRamStart;
			siAddr  &= 0xfffffff8;
			ramAddr &= 0xfffffff8;

#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(SI_STATUS_REG);
#else
			stat = (vu_int)(IO_READ(SI_STATUS_REG));
#endif
			if (!(stat & 
				(SI_STATUS_DMA_BUSY | SI_STATUS_RD_BUSY))) {
				ret = SiTestDma(type, siAddr, ramAddr, 0);
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SiTestDma",
					type, siAddr, ramAddr, nbytes,
					INSERT_RESULT(ret));
				thread->state = IO_STATE_CHECK_STATUS;
			} else {
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SiTestDma",
					type, siAddr, ramAddr, stat, BUSY_STR);
			}
			break;
		}
		case IO_STATE_CHECK_STATUS: {
			/*
			 * Here, we need to combine 2 states into 1 to
			 * protect against an SI IO WR/RD test to come in
			 * between state 2 & 3 and clobber the data (since
			 * SI RAM only contains 64-bytes
			 */
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(SI_STATUS_REG);
#else
			stat = (vu_int)(IO_READ(SI_STATUS_REG));
#endif 
			if (stat != lastStat)
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SiDmaStatus",
					SI_STATUS_REG, SI_STATUS_DMA_BUSY, 
					1, stat, DONE_STR);
			lastStat = stat;
			if (!(stat & SI_STATUS_DMA_BUSY)) {
				if (CheckInterrupt(MI_INTR_SI, &stat)) {
					/* Any write clears interrupt */

#ifdef __sgi__  /* K1--BUG */
					*(vu_int *)PHYS_TO_K1(SI_STATUS_REG)=0;
#else
					IO_WRITE(SI_STATUS_REG, 0);
#endif
					fprintf(LogFp, RTST_MSG_RES2_STR,
						thread - RandThreadTable,
						"SiCheckIntr",
						MI_INTR_REG, MI_INTR_SI,
						0, stat, PASS_STR);
				}
				else {
					fprintf(LogFp, RTST_MSG_RES2_STR,
						thread - RandThreadTable,
						"SiCheckIntr",
						MI_INTR_REG, MI_INTR_SI,
						0, stat, FAIL_STR);
					errorTotal++;
				}

				/* Here we compare the 1st word, last word */
				ret = MemSmplCompare(siAddr,ramAddr,nbytes/4,0);
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable,
					"SiDmaCompare", siAddr, 
					ramAddr, nbytes/4, 0,
					INSERT_RESULT(ret));
				thread->state = IO_STATE_START;
				thread->inProgress = 0;
			}
			break;
		}
		default: {
                        _TRACE(DERROR,
                        fprintf(LogFp,
                                "\tERROR: Illegal IO state encountered!\n"));
		}
	}  /* switch */

}  /* SiRandDma */


/***************************************************************************
 * AI thread routines
 */
void
AiRandDma(ThreadCmd *thread)
{
	int			ret;
	unsigned int		stat;
	static	unsigned int	ramAddr = 0;
	static	unsigned int	nbytes	= 400;
	static	unsigned int	dmaCount = 0;
	static	unsigned int	waitCount = 0;
	static	unsigned int	lastStat  = 0;

	switch (thread->state) {
		case IO_STATE_INIT:
		case IO_STATE_START: {
			thread->inProgress = 1;
			ramAddr = AiRdramStart;

			ret = AiTestDma(ramAddr, nbytes, 0, 0);
			dmaCount++;
			fprintf(LogFp, RTST_MSG_RES2_STR,
				thread - RandThreadTable, "AiTestDma",
				ramAddr, nbytes, 0, 0, INSERT_RESULT(ret));
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(AI_STATUS_REG);
#else
			stat = (vu_int)(IO_READ(AI_STATUS_REG));
#endif
			/* If not full, we start another DMA */
			if (!(stat & AI_STATUS_FIFO_FULL) && 
				(dmaCount < MinRunCount)) {
				ret = AiTestDma(ramAddr, nbytes, 0, 0);
				dmaCount++;
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "AiTestDma",
					ramAddr, nbytes, 0, stat,
					INSERT_RESULT(ret));
			}

			thread->state = IO_STATE_CHECK_STATUS;
			break;
		}
		case IO_STATE_CHECK_STATUS: {
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(AI_STATUS_REG);
#else
			stat = (vu_int)(IO_READ(AI_STATUS_REG));
#endif
			if (stat != lastStat)
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable,
					"AiDmaStatus", 
					AI_STATUS_REG, AI_STATUS_DMA_BUSY, 
					1, stat, DONE_STR);
			lastStat = stat;
			/* If not full, we start another DMA */
			if (!(stat & AI_STATUS_FIFO_FULL) &&
				(dmaCount < MinRunCount)) {
				ret = AiTestDma(ramAddr, nbytes, 0, 0);
				dmaCount++;
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable,
					"AiTestDma", ramAddr, 
					nbytes, 0, 0, INSERT_RESULT(ret));
			}
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(AI_STATUS_REG);
#else
			stat = (vu_int)(IO_READ(AI_STATUS_REG));
#endif
			_TRACE(DSTATUS, 
				fprintf(LogFp, "\n\tStatus = 0x%08x\n",stat));
			if (!(stat & (AI_STATUS_DMA_BUSY|AI_STATUS_FIFO_FULL))){
				if (CheckInterrupt(MI_INTR_AI, &stat)) {
					/* Any write clears interrupt */

#ifdef __sgi__  /* K1--BUG */
					*(vu_int *)PHYS_TO_K1(AI_STATUS_REG)=0;
#else
					IO_WRITE(AI_STATUS_REG, 0);
#endif
					fprintf(LogFp, RTST_MSG_RES2_STR,
						thread - RandThreadTable,
						"AiCheckIntr",
						MI_INTR_REG, MI_INTR_AI,
						0, stat, PASS_STR);
				}
				else {
					fprintf(LogFp, RTST_MSG_RES2_STR,
						thread - RandThreadTable,
						"AiCheckIntr",
						MI_INTR_REG, MI_INTR_AI,
						0, stat, FAIL_STR);
					errorTotal++;
				}

				thread->state = IO_STATE_START;
				thread->inProgress = 0;
			}
			break;
		}
		default: {
                        _TRACE(DERROR,
                        fprintf(LogFp,
                                "\tERROR: Illegal IO state encountered!\n"));
		}
	}  /* switch */

}  /* AiRandDma */


/***************************************************************************
 * VI thread routines
 */
void
ViRandDma(ThreadCmd *thread)
{
	int			ret;
	unsigned int		stat, data;
	static	unsigned int	lastLine = 0;
	static	unsigned int	intrLine = 0;
	static	unsigned int	hWidth   = 0;
	static	unsigned int	ramAddr  = 0;
	static	unsigned int	dmaCount = 0;
	static	unsigned int	done     = 0;
	static	unsigned int	lastStat = 0;

	switch (thread->state) {
		case IO_STATE_INIT:
		case IO_STATE_START: {

			thread->inProgress = 1;

			/* We want RDRAM address to be near 2KB boundary */
			ramAddr = ViRdramStart + 0x400;  /* 0x001fd7e0 */

			lastLine = 0x48;
			intrLine = 0xa;		/* to get intr at line 10 */
			hWidth   = 0x20;	/* 32-32 bit picture */

			/* Assume that VI interrupt mask has been set */

			/* Write-read start RDRAM address */
			ret = MemWriteRead(VI_DRAM_ADDR_REG, ramAddr,
				ramAddr, 0);

			/* Set horizontal width (32x32) */
			ret = MemWriteRead(VI_H_WIDTH_REG, hWidth, hWidth, 0);

			/* Set vertical line interrupt */
			ret = MemWriteRead(VI_V_INTR_REG, intrLine, 
				intrLine, 0);

			/* Write-read timing/burst */
			ret = MemWriteRead(VI_TIMING_REG, 0x820404, 
				0x820404, 0);

			/* Write-read vertical sync */
			ret = MemWriteRead(VI_V_SYNC_REG, lastLine+1, 
				lastLine+1, 0);

			/* Write-read horizontal sync */
			ret = MemWriteRead(VI_H_SYNC_REG, 0x130, 0x130, 0);

			/* Write-read horizontal sync leap */
			ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01300130, 
				0x01300130, 0);

			/* Write-read horizontal start */
			ret = MemWriteRead(VI_H_VIDEO_REG, 0x200040, 
				0x200040, 0);

			/* Write-read vertical start */
			ret = MemWriteRead(VI_V_VIDEO_REG, 0x50045, 
				0x50045, 0);

			/* Write-read vertical burst */
			ret = MemWriteRead(VI_V_BURST_REG, 0x50045, 
				0x50045, 0);

			/* Write-read x-scale */
			ret = MemWriteRead(VI_X_SCALE_REG, 0x400, 
				0x400, 0);

			/* Write-read y-scale */
			ret = MemWriteRead(VI_Y_SCALE_REG, 0x400, 
				0x400, 0);

			/* Write-read controller/status */
			/*
			ret = MemWriteRead(VI_STATUS_REG, 0x303, 0x303, 0);
			*/
			ret = MemWriteRead(VI_STATUS_REG, 0x3003, 
				0x3003, 0);

			/* Write vertical current line */
			ret = MemWrite(VI_V_CURRENT_LINE_REG, 0x0, 0x0, 0);

			/* Read vertical current line */
			ret = MemRead(VI_V_CURRENT_LINE_REG, 0x0, 0x0, 0);

			dmaCount++;
			fprintf(LogFp, RTST_MSG_RES2_STR,
				thread - RandThreadTable,
				"ViTestDma", ramAddr, lastLine,
				intrLine, 0, INSERT_RESULT(ret));

			thread->state = IO_STATE_CHECK_STATUS;
			break;
		}
		case IO_STATE_CHECK_STATUS: {
			/* Check for VI interrupt: should occur at line 
			 * intrLine 
			 */
#ifdef __sgi__  /* K1--BUG */
			data = *(vu_int *)PHYS_TO_K1(MI_INTR_REG);
#else
			data = (vu_int)(IO_READ(MI_INTR_REG));
#endif 
			if (data & MI_INTR_VI) {
				/* Write any to vertical current line 
				 * to clear interrupt
				 */
#ifdef __sgi__  /* K1--BUG */
				*(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG) = 0;
#else
				IO_WRITE(VI_V_CURRENT_LINE_REG, 0);
#endif
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable,
					"ViDmaIntr",
					MI_INTR_REG, data, 0,
					0, DONE_STR);
			}

			/* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
			data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
			data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif
			if (data >= (lastLine & 0xffffffff)) {
#ifdef __sgi__  /* K1--BUG */
				data = *(vu_int *)PHYS_TO_K1(
						VI_V_CURRENT_LINE_REG);
#else
				data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif
				thread->state = IO_STATE_START;
				thread->inProgress = 0;
				done = 1;
			}
			fprintf(LogFp, RTST_MSG_RES2_STR,
				thread - RandThreadTable, "ViDmaCurrent",
				VI_V_CURRENT_LINE_REG, data, lastLine,
				0, DONE_STR);

			break;
		}

		default: {
                        _TRACE(DERROR,
                        fprintf(LogFp,
                                "\tERROR: Illegal IO state encountered!\n"));
		}
	}  /* switch */

}  /* ViRandDma */


#define IO_STATE_CHECK_F0_MLF2  26
#define IO_STATE_CHECK_MID_MLF2 27
#define IO_STATE_CHECK_F1_MLF2  28
#define IO_STATE_CHECK_END_MLF2 29


void ViMLF2Dma(ThreadCmd *thread)
{
    int			ret;
    unsigned int	stat, data;
    int                 dmaCount;
    static unsigned int	ramAddr  = 0;
    static int          done;

    fprintf(stdout, "In ViMLF2Dma procedure \n");

    switch (thread->state) {
	case IO_STATE_INIT:
	case IO_STATE_START: 
	{
	    fprintf(stdout, "In IO_STATE_START \n"); 

	    thread->inProgress = 1;
		    
	    /****************************************************************/
		    
	    /* We want RDRAM address to be near 2KB boundary */
	    /* Advance address by 128 bytes to skip the first field */
	    ramAddr = ViRdramStart + 128;  /* 0x001fd7e0 */

	    /* Write-read start RDRAM address */
	    /* 
	     ret = MemWriteRead(VI_DRAM_ADDR_REG,   0x001f6160, 0x001f6160, 0);
	    */
	    ret = MemWriteRead(VI_DRAM_ADDR_REG,   ramAddr, ramAddr, 0);

	    /* Set horizontal width (32x32) */
	    ret = MemWriteRead(VI_H_WIDTH_REG,     0x00000020, 0x00000020, 0);

	    /* Set vertical line interrupt */
	    ret = MemWriteRead(VI_V_INTR_REG,      0x000003ff, 0x000003ff, 0);

	    /* Write-read timing/burst */
	    ret = MemWriteRead(VI_TIMING_REG,      0x00820404, 0x00820404, 0);

	    /* Write-read vertical sync */
	    ret = MemWriteRead(VI_V_SYNC_REG,      0x0000002A, 0x0000002A, 0);

	    /* Write-read horizontal sync */
	    ret = MemWriteRead(VI_H_SYNC_REG,      0x00000110, 0x00000110, 0);

	    /* Write-read horizontal sync leap */
	    ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01100110, 0x01100110, 0);
 
	    /* Write-read horizontal start */
	    ret = MemWriteRead(VI_H_VIDEO_REG,     0x00200044, 0x00200044, 0);

	    /* Write-read vertical start */
	    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read vertical burst */
	    ret = MemWriteRead(VI_V_BURST_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read x-scale */
	    ret = MemWriteRead(VI_X_SCALE_REG,     0x00000200, 0x00000200, 0);

	    /* Write-read y-scale */
	    ret = MemWriteRead(VI_Y_SCALE_REG,     0x02000400, 0x02000400, 0);

	    /* Write-read controller/status */
            ret = MemWriteRead(VI_STATUS_REG,      0x00003053, 0x00003053, 0);

	    dmaCount++;

	    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
		    "ViMLF2Dma", ramAddr, 0x28, 0x3ff, 0, 
		    INSERT_RESULT(ret));

	    thread->state = IO_STATE_CHECK_F0_MLF2;

	    fprintf(stdout, "Leaving IO_STATE_START \n"); 

	    break;
	}
 
	case IO_STATE_CHECK_F0_MLF2:
	{
	    /* Wait until DMA counter is at end */

#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_MLF2: 0x%.2x \n", data);

	    if (data >= 0x00000028) 
		thread->state = IO_STATE_CHECK_MID_MLF2;

	    break;
	}
	case IO_STATE_CHECK_MID_MLF2:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif


	    fprintf(stdout, "In IO_STATE_CHECK_MID_MLF2: 0x%.2x \n", data);

	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_MLF2;

	    break;		    
	}
	case IO_STATE_CHECK_F1_MLF2:
	{
	    /* Wait until DMA counter is at end */

#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)IO_READ((VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_MLF2: 0x%.2x \n", data);
		    
	    if (data >= 0x00000029)
		thread->state = IO_STATE_CHECK_END_MLF2;

	    break;
	}
	case IO_STATE_CHECK_END_MLF2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_MLF2: 0x%.2x \n", data);

	    if (data < 0x00000029)
		{
		    thread->state = IO_STATE_START;
		    thread->inProgress = 0;
		    done++;
		    fprintf(stdout, "Done = %d \n", done);
		    if (done == 6) 
			{
			    fprintf(stdout, "Finished test \n");
			}
		}

	    break;
	}

	default: 
	{
	    _TRACE(DERROR,
		   fprintf(LogFp,
			   "\tERROR: Illegal IO state encountered!\n"));
	}
	}        /* switch */

} /* ViMLF2Dma */

/* 5 new vi tests */


#define IO_STATE_CHECK_F0_MLN1  5
#define IO_STATE_CHECK_MID_MLN1 6
#define IO_STATE_CHECK_F1_MLN1  7
#define IO_STATE_CHECK_END_MLN1 8

void ViMLN1Dma(ThreadCmd *thread)
{
    int			ret;
    unsigned int	stat, data;
    int                 dmacount;
    static int          done;
    static unsigned int ramAddr = 0;

    switch (thread->state) 
	{
	case IO_STATE_INIT:
	case IO_STATE_START: 
	{
	    fprintf(stdout, "In IO_STATE_START \n"); 
	    fflush(stdout);

	    thread->inProgress = 1;

	    ramAddr = ViRdramStart + 0x400 + 0x40;
		    
	    /****************************************************************/
		    
	    /* Write-read start RDRAM address */
	    ret = MemWriteRead(VI_DRAM_ADDR_REG,      ramAddr,    ramAddr, 0);

	    /* Set horizontal width (32x32) */
	    ret = MemWriteRead(VI_H_WIDTH_REG,     0x00000020, 0x00000020, 0);

	    /* Set vertical line interrupt */
	    ret = MemWriteRead(VI_V_INTR_REG,      0x000003ff, 0x000003ff, 0);

	    /* Write-read timing/burst */
	    ret = MemWriteRead(VI_TIMING_REG,      0x00820404, 0x00820404, 0);

	    /* Write-read vertical sync */
	    ret = MemWriteRead(VI_V_SYNC_REG,      0x00000029, 0x00000029, 0);

	    /* Write-read horizontal sync */
	    ret = MemWriteRead(VI_H_SYNC_REG,      0x00000110, 0x00000110, 0);

	    /* Write-read horizontal sync leap */
	    ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01100110, 0x01100110, 0);
 
	    /* Write-read horizontal start */
	    ret = MemWriteRead(VI_H_VIDEO_REG,     0x00200044, 0x00200044, 0);

	    /* Write-read vertical start */
	    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read vertical burst */
	    ret = MemWriteRead(VI_V_BURST_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read x-scale */
	    ret = MemWriteRead(VI_X_SCALE_REG,     0x00000200, 0x00000200, 0);

	    /* Write-read y-scale */
	    ret = MemWriteRead(VI_Y_SCALE_REG,     0x00000400, 0x00000400, 0);

	    /* Write-read controller/status */
	    ret = MemWriteRead(VI_STATUS_REG,      0x00003112, 0x00003112, 0);

	    dmacount++;

	    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
		    "ViMLN1Dma", 0x1f5820, 0x28, 0x3ff, 0, 
		    INSERT_RESULT(ret));

	    thread->state = IO_STATE_CHECK_F0_MLN1;

	    fprintf(stdout, "Leaving IO_STATE_START \n"); 
	    fflush(stdout);

	    break;
	}
 
	case IO_STATE_CHECK_F0_MLN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_MLN1: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data >= 0x00000028) 
		thread->state = IO_STATE_CHECK_MID_MLN1;

	    break;
	}
	case IO_STATE_CHECK_MID_MLN1:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)IO_READ((VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_MID_MLN1: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_MLN1;

	    break;		    
	}
	case IO_STATE_CHECK_F1_MLN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_MLN1: 0x%.2x \n", data);
	    fflush(stdout);
		    
	    if (data >= 0x00000028)
		thread->state = IO_STATE_CHECK_END_MLN1;

	    break;
	}
	case IO_STATE_CHECK_END_MLN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_MLN1: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000028)
		{
		    thread->state = IO_STATE_CHECK_F0_MLN1;
		    thread->inProgress = 0;
		    done++;
		    printf("Done = %d \n", done);
		    if (done == 5) 
			{
			    QuickDeath = 1;
			    printf("Finished test \n");
			}
		}

	    break;
	}

	default: 
	{
	    _TRACE(DERROR,
		   fprintf(LogFp,
			   "\tERROR: Illegal IO state encountered!\n"));
	}
	}        /* switch */

} /* ViMLN1Dma */

#define IO_STATE_CHECK_F0_MLN2  5
#define IO_STATE_CHECK_MID_MLN2 6
#define IO_STATE_CHECK_F1_MLN2  7
#define IO_STATE_CHECK_END_MLN2 8

void ViMLN2Dma(ThreadCmd *thread)
{
    int			ret;
    unsigned int	stat, data;
    int                 dmacount;
    static int          done;
    static unsigned int ramAddr = 0;

    switch (thread->state) 
	{
	case IO_STATE_INIT:
	case IO_STATE_START: 
	{
	    fprintf(stdout, "In IO_STATE_START \n"); 
	    fflush(stdout);

	    thread->inProgress = 1;
	    ramAddr = ViRdramStart + 0xd00 + 0x80;

		    
	    /****************************************************************/
		    
	    /* Write-read start RDRAM address */
	    ret = MemWriteRead(VI_DRAM_ADDR_REG,      ramAddr,    ramAddr, 0);

	    /* Set horizontal width (32x32) */
	    ret = MemWriteRead(VI_H_WIDTH_REG,     0x00000020, 0x00000020, 0);

	    /* Set vertical line interrupt */
	    ret = MemWriteRead(VI_V_INTR_REG,      0x000003ff, 0x000003ff, 0);

	    /* Write-read timing/burst */
	    ret = MemWriteRead(VI_TIMING_REG,      0x00820404, 0x00820404, 0);

	    /* Write-read vertical sync */
	    ret = MemWriteRead(VI_V_SYNC_REG,      0x00000029, 0x00000029, 0);

	    /* Write-read horizontal sync */
	    ret = MemWriteRead(VI_H_SYNC_REG,      0x00000110, 0x00000110, 0);

	    /* Write-read horizontal sync leap */
	    ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01100110, 0x01100110, 0);
 
	    /* Write-read horizontal start */
	    ret = MemWriteRead(VI_H_VIDEO_REG,     0x00200044, 0x00200044, 0);

	    /* Write-read vertical start */
	    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read vertical burst */
	    ret = MemWriteRead(VI_V_BURST_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read x-scale */
	    ret = MemWriteRead(VI_X_SCALE_REG,     0x00000200, 0x00000200, 0);

	    /* Write-read y-scale */
	    ret = MemWriteRead(VI_Y_SCALE_REG,     0x00000400, 0x00000400, 0);

	    /* Write-read controller/status */
	    ret = MemWriteRead(VI_STATUS_REG,      0x00003013, 0x00003013, 0);

	    dmacount++;

	    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
		    "ViMLN2Dma", 0x1f6160, 0x28, 0x3ff, 0, 
		    INSERT_RESULT(ret));

	    thread->state = IO_STATE_CHECK_F0_MLN2;

	    fprintf(stdout, "Leaving IO_STATE_START \n"); 
	    fflush(stdout);

	    break;
	}
 
	case IO_STATE_CHECK_F0_MLN2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_MLN2: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data >= 0x00000028) 
		thread->state = IO_STATE_CHECK_MID_MLN2;

	    break;
	}
	case IO_STATE_CHECK_MID_MLN2:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_MID_MLN2: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_MLN2;

	    break;		    
	}
	case IO_STATE_CHECK_F1_MLN2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else 
	    data = (vu_int) (IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_MLN2: 0x%.2x \n", data);
	    fflush(stdout);
		    
	    if (data >= 0x00000028)
		thread->state = IO_STATE_CHECK_END_MLN2;

	    break;
	}
	case IO_STATE_CHECK_END_MLN2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else 
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_MLN2: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000028)
		{
		    thread->state = IO_STATE_CHECK_F0_MLN2;
		    thread->inProgress = 0;
		    done++;
		    printf("Done = %d \n", done);
		    if (done == 5) 
			{
			    QuickDeath = 1;
			    printf("Finished test \n");
			}
		}

	    break;
	}

	default: 
	{
	    _TRACE(DERROR,
		   fprintf(LogFp,
			   "\tERROR: Illegal IO state encountered!\n"));
	}
	}        /* switch */

} /* ViMLN2Dma */

#define IO_STATE_CHECK_F0_MLP1  5
#define IO_STATE_CHECK_MID_MLP1 6
#define IO_STATE_CHECK_F1_MLP1  7
#define IO_STATE_CHECK_END_MLP1 8

void ViMLP1Dma(ThreadCmd *thread)
{
    int			ret;
    unsigned int	stat, data;
    int                 dmacount;
    static int          done;
    static unsigned int ramAddr = 0;

    switch (thread->state) 
	{
	case IO_STATE_INIT:
	case IO_STATE_START: 
	{
	    fprintf(stdout, "In IO_STATE_START \n"); 
	    fflush(stdout);

	    thread->inProgress = 1;
	    ramAddr = ViRdramStart + 0x1d00 + 0x40;
		    
	    /****************************************************************/
		    
	    /* Write-read start RDRAM address */
	    ret = MemWriteRead(VI_DRAM_ADDR_REG,      ramAddr,    ramAddr, 0);

	    /* Set horizontal width (32x32) */
	    ret = MemWriteRead(VI_H_WIDTH_REG,     0x00000020, 0x00000020, 0);

	    /* Set vertical line interrupt */
	    ret = MemWriteRead(VI_V_INTR_REG,      0x000003ff, 0x000003ff, 0);

	    /* Write-read timing/burst */
	    ret = MemWriteRead(VI_TIMING_REG,      0x00820404, 0x00820404, 0);

	    /* Write-read vertical sync */
	    ret = MemWriteRead(VI_V_SYNC_REG,      0x00000029, 0x00000029, 0);

	    /* Write-read horizontal sync */
	    ret = MemWriteRead(VI_H_SYNC_REG,      0x00000100, 0x00000100, 0);

	    /* Write-read horizontal sync leap */
	    ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01000100, 0x01000100, 0);
 
	    /* Write-read horizontal start */
	    ret = MemWriteRead(VI_H_VIDEO_REG,     0x00200040, 0x00200040, 0);

	    /* Write-read vertical start */
	    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read vertical burst */
	    ret = MemWriteRead(VI_V_BURST_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read x-scale */
	    ret = MemWriteRead(VI_X_SCALE_REG,     0x00000200, 0x00000200, 0);

	    /* Write-read y-scale */
	    ret = MemWriteRead(VI_Y_SCALE_REG,     0x00000400, 0x00000400, 0);

	    /* Write-read controller/status */
	    ret = MemWriteRead(VI_STATUS_REG,      0x00003302, 0x00003302, 0);

	    dmacount++;

	    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
		    "ViMLP1Dma", 0x1f7120, 0x28, 0x3ff, 0, 
		    INSERT_RESULT(ret));

	    thread->state = IO_STATE_CHECK_F0_MLP1;

	    fprintf(stdout, "Leaving IO_STATE_START \n"); 
	    fflush(stdout);

	    break;
	}
 
	case IO_STATE_CHECK_F0_MLP1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)IO_READ(VI_V_CURRENT_LINE_REG);
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_MLP1: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data >= 0x00000028) 
		thread->state = IO_STATE_CHECK_MID_MLP1;

	    break;
	}
	case IO_STATE_CHECK_MID_MLP1:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_MID_MLP1: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_MLP1;

	    break;		    
	}
	case IO_STATE_CHECK_F1_MLP1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_MLP1: 0x%.2x \n", data);
	    fflush(stdout);
		    
	    if (data >= 0x00000028)
		thread->state = IO_STATE_CHECK_END_MLP1;

	    break;
	}
	case IO_STATE_CHECK_END_MLP1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif 

	    fprintf(stdout, "In IO_STATE_CHECK_END_MLP1: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000028)
		{
		    thread->state = IO_STATE_CHECK_F0_MLP1;
		    thread->inProgress = 0;
		    done++;
		    printf("Done = %d \n", done);
		    if (done == 5) 
			{
			    QuickDeath = 1;
			    printf("Finished test \n");
			}
		}

	    break;
	}

	default: 
	{
	    _TRACE(DERROR,
		   fprintf(LogFp,
			   "\tERROR: Illegal IO state encountered!\n"));
	}
	}        /* switch */

} /* ViMLP1Dma */

#define IO_STATE_CHECK_F0_MHN1  5
#define IO_STATE_CHECK_MID_MHN1 6
#define IO_STATE_CHECK_F1_MHN1  7
#define IO_STATE_CHECK_END_MHN1 8

void ViMHN1Dma(ThreadCmd *thread)
{
    int			ret;
    unsigned int	stat, data;
    int                 dmacount;
    static int          done;
    static unsigned int ramAddr = 0;

    switch (thread->state) 
	{
	case IO_STATE_INIT:
	case IO_STATE_START: 
	{
	    fprintf(stdout, "In IO_STATE_START \n"); 
	    fflush(stdout);

	    thread->inProgress = 1;
	    ramAddr = ViRdramStart + 0x27d0 + 0x80;

		    
	    /****************************************************************/
		    
	    /* Write-read start RDRAM address */
	    ret = MemWriteRead(VI_DRAM_ADDR_REG,      ramAddr,    ramAddr, 0);

	    /* Set horizontal width (32x32) */
	    ret = MemWriteRead(VI_H_WIDTH_REG,     0x00000040, 0x00000040, 0);

	    /* Set vertical line interrupt */
	    ret = MemWriteRead(VI_V_INTR_REG,      0x000003ff, 0x000003ff, 0);

	    /* Write-read timing/burst */
	    ret = MemWriteRead(VI_TIMING_REG,      0x00820404, 0x00820404, 0);

	    /* Write-read vertical sync */
	    ret = MemWriteRead(VI_V_SYNC_REG,      0x0000002a, 0x0000002a, 0);

	    /* Write-read horizontal sync */
	    ret = MemWriteRead(VI_H_SYNC_REG,      0x00000110, 0x00000110, 0);

	    /* Write-read horizontal sync leap */
	    ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01100110, 0x01100110, 0);
 
	    /* Write-read horizontal start */
	    ret = MemWriteRead(VI_H_VIDEO_REG,     0x00200044, 0x00200044, 0);

	    /* Write-read vertical start */
	    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read vertical burst */
	    ret = MemWriteRead(VI_V_BURST_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read x-scale */
	    ret = MemWriteRead(VI_X_SCALE_REG,     0x00000400, 0x00000400, 0);

	    /* Write-read y-scale */
	    ret = MemWriteRead(VI_Y_SCALE_REG,     0x00000400, 0x00000400, 0);

	    /* Write-read controller/status */
	    ret = MemWriteRead(VI_STATUS_REG,      0x00003052, 0x00003052, 0);

	    dmacount++;

	    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
		    "ViMHN1Dma", 0x1f7c30, 0x28, 0x3ff, 0, 
		    INSERT_RESULT(ret));

	    thread->state = IO_STATE_CHECK_F0_MHN1;

	    fprintf(stdout, "Leaving IO_STATE_START \n"); 
	    fflush(stdout);

	    break;
	}
 
	case IO_STATE_CHECK_F0_MHN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_MHN1: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data >= 0x00000028) 
		thread->state = IO_STATE_CHECK_MID_MHN1;

	    break;
	}
	case IO_STATE_CHECK_MID_MHN1:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_MID_MHN1: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_MHN1;

	    break;		    
	}
	case IO_STATE_CHECK_F1_MHN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_MHN1: 0x%.2x \n", data);
	    fflush(stdout);
		    
	    if (data >= 0x00000028)
		thread->state = IO_STATE_CHECK_END_MHN1;

	    break;
	}
	case IO_STATE_CHECK_END_MHN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_MHN1: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000028)
		{
		    thread->state = IO_STATE_CHECK_F0_MHN1;
		    thread->inProgress = 0;
		    done++;
		    printf("Done = %d \n", done);
		    if (done == 5) 
			{
			    QuickDeath = 1;
			    printf("Finished test \n");
			}
		}

	    break;
	}

	default: 
	{
	    _TRACE(DERROR,
		   fprintf(LogFp,
			   "\tERROR: Illegal IO state encountered!\n"));
	}
	}        /* switch */

} /* ViMHN1Dma */

#define IO_STATE_CHECK_F0_MHF2  5
#define IO_STATE_CHECK_MID_MHF2 6
#define IO_STATE_CHECK_F1_MHF2  7
#define IO_STATE_CHECK_END_MHF2 8

void ViMHF2Dma(ThreadCmd *thread)
{
    int			ret;
    unsigned int	stat, data;
    int                 dmacount;
    static int          done;
     static unsigned int ramAddr = 0;

    switch (thread->state) 
	{
	case IO_STATE_INIT:
	case IO_STATE_START: 
	{
	    fprintf(stdout, "In IO_STATE_START \n"); 
	    fflush(stdout);

	    thread->inProgress = 1;
	    ramAddr = ViRdramStart + 0x3120 + 0x80;
 		    
	    /****************************************************************/
		    
	    /* Write-read start RDRAM address */
	    ret = MemWriteRead(VI_DRAM_ADDR_REG,      ramAddr,    ramAddr, 0);

	    /* Set horizontal width (32x32) */
	    ret = MemWriteRead(VI_H_WIDTH_REG,     0x00000020, 0x00000020, 0);

	    /* Set vertical line interrupt */
	    ret = MemWriteRead(VI_V_INTR_REG,      0x000003ff, 0x000003ff, 0);

	    /* Write-read timing/burst */
	    ret = MemWriteRead(VI_TIMING_REG,      0x00820404, 0x00820404, 0);

	    /* Write-read vertical sync */
	    ret = MemWriteRead(VI_V_SYNC_REG,      0x0000002a, 0x0000002a, 0);

	    /* Write-read horizontal sync */
	    ret = MemWriteRead(VI_H_SYNC_REG,      0x00000110, 0x00000110, 0);

	    /* Write-read horizontal sync leap */
	    ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01100110, 0x01100110, 0);
 
	    /* Write-read horizontal start */
	    ret = MemWriteRead(VI_H_VIDEO_REG,     0x00200044, 0x00200044, 0);

	    /* Write-read vertical start */
	    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read vertical burst */
	    ret = MemWriteRead(VI_V_BURST_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read x-scale */
	    ret = MemWriteRead(VI_X_SCALE_REG,     0x00000400, 0x00000400, 0);

	    /* Write-read y-scale */
	    ret = MemWriteRead(VI_Y_SCALE_REG,     0x02000800, 0x02000800, 0);

	    /* Write-read controller/status */
	    ret = MemWriteRead(VI_STATUS_REG,      0x00003243, 0x00003243, 0);

	    dmacount++;

	    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
		    "ViMHF2Dma", 0x1f5820, 0x28, 0x3ff, 0, 
		    INSERT_RESULT(ret));

	    thread->state = IO_STATE_CHECK_F0_MHF2;

	    fprintf(stdout, "Leaving IO_STATE_START \n"); 
	    fflush(stdout);

	    break;
	}
 
	case IO_STATE_CHECK_F0_MHF2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_MHF2: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data >= 0x00000028) 
		thread->state = IO_STATE_CHECK_MID_MHF2;

	    break;
	}
	case IO_STATE_CHECK_MID_MHF2:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
            data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_MID_MHF2: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_MHF2;

	    break;		    
	}
	case IO_STATE_CHECK_F1_MHF2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_MHF2: 0x%.2x \n", data);
	    fflush(stdout);
		    
	    if (data >= 0x00000028)
		thread->state = IO_STATE_CHECK_END_MHF2;

	    break;
	}
	case IO_STATE_CHECK_END_MHF2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_MHF2: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000028)
		{
		    thread->state = IO_STATE_CHECK_F0_MHF2;
		    thread->inProgress = 0;
		    done++;
		    printf("Done = %d \n", done);
		    if (done == 5) 
			{
			    QuickDeath = 1;
			    printf("Finished test \n");
			}
		}

	    break;
	}

	default: 
	{
	    _TRACE(DERROR,
		   fprintf(LogFp,
			   "\tERROR: Illegal IO state encountered!\n"));
	}
	}        /* switch */

} /* ViMHF2Dma */

void ViBigDma(ThreadCmd *thread)
{
    int			ret;
    unsigned int		stat, data;
    static	unsigned int	lastLine = 0;
    static	unsigned int	intrLine = 0;
    static	unsigned int	hWidth   = 0;
    static	unsigned int	ramAddr  = 0;
    static	unsigned int	dmaCount = 0;
    static	unsigned int	done     = 0;
    static	unsigned int	lastStat = 0;
    
    printf("In ViBigDma procedure \n");

    switch (thread->state) 
	{
	case IO_STATE_INIT:
	case IO_STATE_START: 
	{
	    fprintf(stdout, "In IO_STATE_START \n"); 
	    fflush(stdout);

	    thread->inProgress = 1;

	    ramAddr = ViRdramStart;  /* 0x001f53e0 */

	    lastLine = 0x28;
	    intrLine = 0x3ff;	/* disable interrupt   */
	    hWidth   = 0x20;	/* 32 pixel wide image */

	    /* Do the global register settings that are going to be
	       constant throughout the test */
		    
	    /* Set vertical line interrupt */
	    ret = MemWriteRead(VI_V_INTR_REG,      0x000003ff, 0x000003ff, 0);

	    /* Write-read timing/burst */
	    ret = MemWriteRead(VI_TIMING_REG,      0x00820404, 0x00820404, 0);

	    /* Write-read vertical burst */
	    ret = MemWriteRead(VI_V_BURST_REG,     0x00050025, 0x00050025, 0);
 
	    /****************************************************************/
	    /* File: vi_lan1.tst */

	    /* Write-read horizontal sync */
	    ret = MemWriteRead(VI_H_SYNC_REG,      0x00000110, 0x00000110, 0);

	    /* Write-read horizontal sync leap */
	    ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01100110, 0x01100110, 0);
 
	    /* Write-read vertical sync */
	    ret = MemWriteRead(VI_V_SYNC_REG,      0x00000029, 0x00000029, 0);

	    /* Set horizontal width (32x32) */
	    ret = MemWriteRead(VI_H_WIDTH_REG,     0x00000020, 0x00000020, 0);

	    /* Write-read horizontal start */
	    ret = MemWriteRead(VI_H_VIDEO_REG,     0x00200044, 0x00200044, 0);

	    /* Write-read vertical start */
	    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read start RDRAM address */
	    ret = MemWriteRead(VI_DRAM_ADDR_REG,   0x001f5820, 0x001f5820, 0);

	    /* Write-read x-scale */
	    ret = MemWriteRead(VI_X_SCALE_REG,     0x00000200, 0x00000200, 0);

	    /* Write-read y-scale */
	    ret = MemWriteRead(VI_Y_SCALE_REG,     0x00000400, 0x00000400, 0);

	    /* Write-read controller/status */
	    ret = MemWriteRead(VI_STATUS_REG,      0x00000112, 0x00000112, 0);

	    dmaCount++;

	    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
		    "ViTestDma", ramAddr, lastLine, intrLine, 0, 
		    INSERT_RESULT(ret));

	    thread->state = IO_STATE_CHECK_F0_LAN1;

	    fprintf(stdout, "Leaving IO_STATE_START \n"); 
	    fflush(stdout);

	    break;
	}
	case IO_STATE_CHECK_F0_LAN1: 
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "IO_STATE_CHECK_F0_LAN1: 0x%.2x \n", data); 
	    fflush(stdout);
			   
		    
	    if (data >= 0x00000028) 
		thread->state = IO_STATE_CHECK_MID_LAN1;

	    break;
	}
	case IO_STATE_CHECK_MID_LAN1:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else	
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_MID_LAN1: 0x%.2x \n", data); 
	    fflush(stdout);


	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_LAN1;

	    break;
		    
	}
	case IO_STATE_CHECK_F1_LAN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_LAN1: 0x%.2x \n", data); 
	    fflush(stdout);


	    if (data >= 0x00000028)
		thread->state = IO_STATE_CHECK_END_LAN1;

	    break;
	}
	case IO_STATE_CHECK_END_LAN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_LAN1 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000028)
		{
		    /* Init registers for lan2 test */

		    /* Write-read start RDRAM address */
		    ret = MemWriteRead(VI_DRAM_ADDR_REG,   0x001f6160, 0x001f6160, 0);

		    /* Write-read controller/status */
		    ret = MemWriteRead(VI_STATUS_REG,      0x00000013, 0x00000013, 0);

		    dmaCount++;

		    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
			    "ViTestDma", ramAddr, lastLine, intrLine, 0, 
			    INSERT_RESULT(ret));

		    thread->state = IO_STATE_CHECK_F0_LAN2;
		}

	    break;
	}

	case IO_STATE_CHECK_F0_LAN2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_LAN2: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data >= 0x00000028) 
		thread->state = IO_STATE_CHECK_MID_LAN2;

	    break;
	}
	case IO_STATE_CHECK_MID_LAN2:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_MID_LAN2: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_LAN2;

	    break;		    
	}
	case IO_STATE_CHECK_F1_LAN2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int )(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_LAN2: 0x%.2x \n", data);
	    fflush(stdout);
		    

	    if (data >= 0x00000028)
		thread->state = IO_STATE_CHECK_END_LAN2;

	    break;
	}
	case IO_STATE_CHECK_END_LAN2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_LAN2: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data < 0x00000028)
		{
		    /* Init registers for lpn1 test */

		    /* Write-read horizontal sync */
		    ret = MemWriteRead(VI_H_SYNC_REG,      0x00000100, 0x00000100, 0);

		    /* Write-read horizontal sync leap */
		    ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01000100, 0x01000100, 0);
 
		    /* Write-read horizontal start */
		    ret = MemWriteRead(VI_H_VIDEO_REG,     0x00200040, 0x00200040, 0);

		    /* Write-read start RDRAM address */
		    ret = MemWriteRead(VI_DRAM_ADDR_REG,   0x001f7120, 0x001f7120, 0);

		    /* Write-read controller/status */
		    ret = MemWriteRead(VI_STATUS_REG,      0x00000302, 0x00000302, 0);

		    dmaCount++;

		    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
			    "ViTestDma", ramAddr, lastLine, intrLine, 0, 
			    INSERT_RESULT(ret));

		    thread->state = IO_STATE_CHECK_F0_LPN1;
		}

	    break;
	}
	case IO_STATE_CHECK_F0_LPN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_LPN1: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data >= 0x00000028) 
		thread->state = IO_STATE_CHECK_MID_LPN1;

	    break;
	}
	case IO_STATE_CHECK_MID_LPN1:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_MID_LPN1: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_LPN1;

	    break;		    
	}
	case IO_STATE_CHECK_F1_LPN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_LPN1: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data >= 0x00000028)
		thread->state = IO_STATE_CHECK_END_LPN1;

	    break;
	}
	case IO_STATE_CHECK_END_LPN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
            data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_LPN1: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data < 0x00000028)
		{
		    /* Init registers for han1 test */

		    /* Write-read horizontal sync */
		    ret = MemWriteRead(VI_H_SYNC_REG,      0x00000110, 0x00000110, 0);
			    
		    /* Write-read horizontal sync leap */
		    ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01100110, 0x01100110, 0);

		    /* Write-read vertical sync */
		    ret = MemWriteRead(VI_V_SYNC_REG,      0x0000002A, 0x0000002A, 0);

		    /* Set horizontal width (32x32) */
		    ret = MemWriteRead(VI_H_WIDTH_REG,     0x00000040, 0x00000040, 0);

		    /* Write-read horizontal start */
		    ret = MemWriteRead(VI_H_VIDEO_REG,     0x00200044, 0x00200044, 0);

		    /* Write-read start RDRAM address */
		    ret = MemWriteRead(VI_DRAM_ADDR_REG,   0x001f7c30, 0x001f7c30, 0);

		    /* Write-read x-scale */
		    ret = MemWriteRead(VI_X_SCALE_REG,     0x00000400, 0x00000400, 0);

		    /* Write-read controller/status */
		    ret = MemWriteRead(VI_STATUS_REG,      0x00000052, 0x00000052, 0);

		    dmaCount++;

		    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
			    "ViTestDma", ramAddr, lastLine, intrLine, 0, 
			    INSERT_RESULT(ret));

		    thread->state = IO_STATE_CHECK_F0_HAN1;
		}
			
	    break;
	}

	case IO_STATE_CHECK_F0_HAN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_HAN1: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data >= 0x00000028) 
		{
		    /* Write-read start RDRAM address */
		    ret = MemWriteRead(VI_DRAM_ADDR_REG,   0x001f7c70, 0x001f7c70, 0);
			    
		    /* Write-read vertical start */
		    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00070027, 0x00070027, 0);

		    thread->state = IO_STATE_CHECK_MID_HAN1;
		}

	    break;
	}
	case IO_STATE_CHECK_MID_HAN1:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif
	    fprintf(stdout, "In IO_STATE_CHECK_MID_HAN1: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_HAN1;

	    break;		    
	}
	case IO_STATE_CHECK_F1_HAN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_HAN1: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data >= 0x00000029)
		thread->state = IO_STATE_CHECK_END_HAN1;

	    break;
	}
	case IO_STATE_CHECK_END_HAN1:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int )(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_HAN1: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data < 0x00000029)
		{
		    /* Init registers for hpf2 test */

		    /* Set horizontal width (32x32) */
		    ret = MemWriteRead(VI_H_WIDTH_REG,     0x00000020, 0x00000020, 0);

		    /* Write-read start RDRAM address */
		    ret = MemWriteRead(VI_DRAM_ADDR_REG,   0x001f8580, 0x001f8580, 0);

		    /* Write-read vertical start */
		    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00050025, 0x00050025, 0);

		    /* Write-read y-scale */
		    ret = MemWriteRead(VI_Y_SCALE_REG,     0x02000800, 0x02000800, 0);

		    /* Write-read controller/status */
		    ret = MemWriteRead(VI_STATUS_REG,      0x00000243, 0x00000243, 0);

		    dmaCount++;

		    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
			    "ViTestDma", ramAddr, lastLine, intrLine, 0, 
			    INSERT_RESULT(ret));

		    thread->state = IO_STATE_CHECK_F0_HPF2;
		}

	    break;
	}

	case IO_STATE_CHECK_F0_HPF2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_HPF2: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data >= 0x00000028) 
		{
		    /* Write-read start RDRAM address */
		    ret = MemWriteRead(VI_DRAM_ADDR_REG,   0x001f8600, 0x001f8600, 0);
			    
		    /* Write-read vertical start */
		    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00070027, 0x00070027, 0);
			   
		    thread->state = IO_STATE_CHECK_MID_HPF2;
		}

	    break;
	}
	case IO_STATE_CHECK_MID_HPF2:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_MID_HPF2: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_HPF2;

	    break;		    
	}

	case IO_STATE_CHECK_F1_HPF2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_HPF2: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data >= 0x00000029)
		thread->state = IO_STATE_CHECK_END_HPF2;

	    break;
	}
	case IO_STATE_CHECK_END_HPF2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_HPF2: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000029) 
		{
		    thread->state = IO_STATE_START;
		    thread->inProgress = 0;
		    done = 1;
		    QuickDeath = 1;
		    printf("Finished test \n");
		}

	    break;
	}
	default: 
	{
	    _TRACE(DERROR, 
		   fprintf(LogFp,
			   "\tERROR: Illegal IO state encountered!\n"));
	}
	}  /* switch */

} /* ViBigDma */


void ViLan2Dma(ThreadCmd *thread)
{
    int			ret;
    unsigned int	stat, data;
    int                 dmacount;
    int                 done;

    printf("In ViLan2Dma procedure \n");

    switch (thread->state) 
	{
	case IO_STATE_INIT:
	case IO_STATE_START: 
	{
	    fprintf(stdout, "In IO_STATE_START \n"); 
	    fflush(stdout);

	    thread->inProgress = 1;
		    
	    /****************************************************************/
	    /* File: vi_lan2.tst */
		    
	    /* Write-read start RDRAM address */
	    ret = MemWriteRead(VI_DRAM_ADDR_REG,   0x001f6160, 0x001f6160, 0);

	    /* Set horizontal width (32x32) */
	    ret = MemWriteRead(VI_H_WIDTH_REG,     0x00000020, 0x00000020, 0);

	    /* Set vertical line interrupt */
	    ret = MemWriteRead(VI_V_INTR_REG,      0x000003ff, 0x000003ff, 0);

	    /* Write-read timing/burst */
	    ret = MemWriteRead(VI_TIMING_REG,      0x00820404, 0x00820404, 0);

	    /* Write-read vertical sync */
	    ret = MemWriteRead(VI_V_SYNC_REG,      0x00000029, 0x00000029, 0);

	    /* Write-read horizontal sync */
	    ret = MemWriteRead(VI_H_SYNC_REG,      0x00000110, 0x00000110, 0);

	    /* Write-read horizontal sync leap */
	    ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01100110, 0x01100110, 0);
 
	    /* Write-read horizontal start */
	    ret = MemWriteRead(VI_H_VIDEO_REG,     0x00200044, 0x00200044, 0);

	    /* Write-read vertical start */
	    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read vertical burst */
	    ret = MemWriteRead(VI_V_BURST_REG,     0x00050025, 0x00050025, 0);

	    /* Write-read x-scale */
	    ret = MemWriteRead(VI_X_SCALE_REG,     0x00000200, 0x00000200, 0);

	    /* Write-read y-scale */
	    ret = MemWriteRead(VI_Y_SCALE_REG,     0x00000400, 0x00000400, 0);

	    /* Write-read controller/status */
	    ret = MemWriteRead(VI_STATUS_REG,      0x00000013, 0x00000013, 0);

	    dmacount++;

	    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
		    "ViLan2Dma", 0x1f6160, 0x28, 0x3ff, 0, 
		    INSERT_RESULT(ret));

	    thread->state = IO_STATE_CHECK_F0_LAN2;

	    fprintf(stdout, "Leaving IO_STATE_START \n"); 
	    fflush(stdout);

	    break;
	}
 
	case IO_STATE_CHECK_F0_LAN2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_LAN2: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data >= 0x00000028) 
		thread->state = IO_STATE_CHECK_MID_LAN2;

	    break;
	}
	case IO_STATE_CHECK_MID_LAN2:
	{
	    /* Wait until DMA counter is back at beginning  */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_MID_LAN2: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data < 0x00000028) 
		thread->state = IO_STATE_CHECK_F1_LAN2;

	    break;		    
	}
	case IO_STATE_CHECK_F1_LAN2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F1_LAN2: 0x%.2x \n", data);
	    fflush(stdout);
		    

	    if (data >= 0x00000028)
		thread->state = IO_STATE_CHECK_END_LAN2;

	    break;
	}
	case IO_STATE_CHECK_END_LAN2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int )(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_LAN2: 0x%.2x \n", data);
	    fflush(stdout);


	    if (data < 0x00000028)
		{
		    thread->state = IO_STATE_START;
		    thread->inProgress = 0;
		    done = 1;
		    QuickDeath = 1;
		    printf("Finished test \n");
		}

	    break;
	}

	default: 
	{
	    _TRACE(DERROR,
		   fprintf(LogFp,
			   "\tERROR: Illegal IO state encountered!\n"));
	}
	}        /* switch */

} /* ViLan2Dma */

#define IO_STATE_CHECK_F0_DTH2  5
#define IO_STATE_CHECK_MID_DTH2 6
#define IO_STATE_CHECK_F1_DTH2  7
#define IO_STATE_CHECK_END_DTH2 8

void ViDTH2Dma(ThreadCmd *thread)
{
    int			ret;
    unsigned int	stat, data;
    int                 dmacount;
    static int          done;
     static unsigned int ramAddr = 0;

    switch (thread->state) 
	{
	case IO_STATE_INIT:
	case IO_STATE_START: 
	{
	    fprintf(stdout, "In IO_STATE_START \n"); 
	    fprintf(stdout, "Address -> 0x%.8x \n", ViRdramStart);
	    fflush(stdout);

	    thread->inProgress = 1;
	    ramAddr = ViRdramStart;
	    
	    /****************************************************************/
		    
	    /* Write-read start RDRAM address */
	    ret = MemWriteRead(VI_DRAM_ADDR_REG,      ramAddr,    ramAddr, 0);

	    /* Set horizontal width (32x32) */
	    ret = MemWriteRead(VI_H_WIDTH_REG,     0x00000020, 0x00000020, 0);

	    /* Set vertical line interrupt */
	    ret = MemWriteRead(VI_V_INTR_REG,      0x000003ff, 0x000003ff, 0);

	    /* Write-read timing/burst */
	    ret = MemWriteRead(VI_TIMING_REG,      0x00820404, 0x00820404, 0);

	    /* Write-read vertical sync */
	    ret = MemWriteRead(VI_V_SYNC_REG,      0x00000049, 0x00000049, 0);

	    /* Write-read horizontal sync */
	    ret = MemWriteRead(VI_H_SYNC_REG,      0x00000110, 0x00000110, 0);

	    /* Write-read horizontal sync leap */
	    ret = MemWriteRead(VI_H_SYNC_LEAP_REG, 0x01100110, 0x01100110, 0);
 
	    /* Write-read horizontal start */
	    ret = MemWriteRead(VI_H_VIDEO_REG,     0x00200044, 0x00200044, 0);

	    /* Write-read vertical start */
	    ret = MemWriteRead(VI_V_VIDEO_REG,     0x00050045, 0x00050045, 0);

	    /* Write-read vertical burst */
	    ret = MemWriteRead(VI_V_BURST_REG,     0x00050045, 0x00050045, 0);

	    /* Write-read x-scale */
	    ret = MemWriteRead(VI_X_SCALE_REG,     0x00000400, 0x00000400, 0);

	    /* Write-read y-scale */
	    ret = MemWriteRead(VI_Y_SCALE_REG,     0x00000400, 0x00000400, 0);

	    /* Write-read controller/status */
	    ret = MemWriteRead(VI_STATUS_REG,      0x00013003, 0x00013003, 0);

	    dmacount++;

	    fprintf(LogFp, RTST_MSG_RES2_STR, thread - RandThreadTable,
		    "ViDTH2Dma", 0x1f5820, 0x48, 0x3ff, 0, 
		    INSERT_RESULT(ret));

	    thread->state = IO_STATE_CHECK_F0_DTH2;

	    fprintf(stdout, "Leaving IO_STATE_START \n"); 
	    fflush(stdout);

	    break;
	}
 
	case IO_STATE_CHECK_F0_DTH2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_F0_DTH2: 0x%.2x \n", data);
	    fflush(stdout);

	    /* We only do 1 frame, every frame is the same */
	    if (data >= 0x00000048) 
		thread->state = IO_STATE_CHECK_END_DTH2;

	    break;
	}
	case IO_STATE_CHECK_END_DTH2:
	{
	    /* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
	    data = *(vu_int *)PHYS_TO_K1(VI_V_CURRENT_LINE_REG);
#else
	    data = (vu_int)(IO_READ(VI_V_CURRENT_LINE_REG));
#endif

	    fprintf(stdout, "In IO_STATE_CHECK_END_DTH2: 0x%.2x \n", data);
	    fflush(stdout);

	    if (data < 0x00000048)
		{
		    thread->state = IO_STATE_CHECK_F0_DTH2;
		    thread->inProgress = 0;
		    done++;
		    printf("Done = %d \n", done);
		    if (done == 5) 
			{
			    QuickDeath = 1;
			    printf("Finished test \n");
			}
		}

	    break;
	}

	default: 
	{
	    _TRACE(DERROR,
		   fprintf(LogFp,
			   "\tERROR: Illegal IO state encountered!\n"));
	}
	}        /* switch */

} /* ViDTH2Dma */



/***************************************************************************
 * SP thread routines
 */
static int
getSpSemaphore(void)
{
	unsigned int sem;

#ifdef __sgi__  /* K1--BUG */
	sem = *(vu_int *)PHYS_TO_K1(SP_SEMAPHORE_REG);
#else
	sem = (vu_int)(IO_READ(SP_SEMAPHORE_REG));
#endif

	/* If sem is 0, it means that we have the semaphore */
	return((sem == 0) ? 1 : 0);
}

static void
releaseSpSemaphore(void)
{
#ifdef __sgi__  /* K1--BUG */
	*(vu_int *)PHYS_TO_K1(SP_SEMAPHORE_REG) = 0;
#else
	IO_WRITE(SP_SEMAPHORE_REG, 0);
#endif
}

void
SpRandIoRd(ThreadCmd *thread)
{
	unsigned int		data;
	unsigned int		stat;
	char			s1[20];
	static unsigned int 	address = 0;

	/* Assume that ROM has been initialized with data = address */
	if ((address == 0) || (address == SpImemStart)) {
		address = SpDmemStart;
	}
	else if (address == SpDmemStart) {
		address = SpImemStart;
	}
	address = address & 0xfffffffc;

	/* 
	 * For SP, we need to check for IO full bit before perform
	 * IO read - If they're busy, we simply exit and try again 
	 * later
	 */
#ifdef __sgi__  /* K1--BUG */
	stat = *(vu_int *)PHYS_TO_K1(SP_STATUS_REG);
#else
	stat = (vu_int)(IO_READ(SP_STATUS_REG));
#endif
	if ((stat & SP_STATUS_IO_FULL) ||
	    ((address == SpImemStart) && !(stat & SP_STATUS_HALT))) {
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, data, 0, stat, BUSY_STR);
	}
	else {
		data = IoSpRead(address);
		sprintf(s1, "0x%08x", data); 
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, data, 0, stat, s1);
	}

}  /* SpRandIoRd */


void
SpRandIoWrRd(ThreadCmd *thread)
{
	int			ret;
	unsigned int		stat;
	static unsigned int	address = 0;

	/* 
	 * For SP, we need to check for DMA/IO busy bits before perform
	 * IO write - If they're busy, we simply exit and try again 
	 * later
	 */
	/* Reserve the 1st 32-bit for IO read */
	if ((address == 0) || (address == SpImemStart+8)) {
		address = SpDmemStart+8;
	}
	else if (address == SpDmemStart+8) {
		address = SpImemStart+8;
	}
	address = address & 0xfffffffc;

#ifdef __sgi__  /* K1--BUG */
	stat = *(vu_int *)PHYS_TO_K1(SP_STATUS_REG);
#else
	stat = (vu_int)(IO_READ(SP_STATUS_REG));
#endif
	if ((stat & (SP_STATUS_DMA_BUSY | SP_STATUS_IO_FULL)) ||
	    ((address == SpImemStart+8) && !(stat & SP_STATUS_HALT))) {
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, address, 0, 0, BUSY_STR);
	}
	else {
		ret = SpTestIoWrite(address, address, 0, 0);
		fprintf(LogFp, RTST_MSG_RES2_STR,
			thread - RandThreadTable, thread->name,
			address, address, 0, stat, INSERT_RESULT(ret));
	}

}  /* SpRandIoWrRd */


void
SpRandDma(ThreadCmd *thread)
{
	int			i, ret;
	unsigned int		stat;
	static	unsigned int	skip, count, nbytes;
	static	unsigned int	dir      = DIR_TO_RAM;
	static	unsigned int	spAddr   = 0;
	static	unsigned int	ramAddr  = 0;
	static	unsigned int	length	 = IMEM_TEST_SIZE - 16;
	static	unsigned int	lastStat = 0;

	switch (thread->state) {
		case IO_STATE_INIT: 
		case IO_STATE_START: {
			thread->inProgress = 1;

			/* Toggle 
			dir = (dir==DIR_TO_RAM) ? DIR_FROM_RAM : DIR_TO_RAM;

			/* Toggle between I/DMEM address 
			 * Reserve the first 2 words (64-bit) for IO W/R
			 */
			if (spAddr == SpImemStart+16)
				spAddr = SpDmemStart+16;
			else {
				spAddr = SpImemStart+16;
				/* For IMEM, we only DMA RDRAM -> IMEM */
				dir = DIR_FROM_RAM; 
			}
			ramAddr = (dir == DIR_FROM_RAM) ? SpRdramStart :
					(SpRdramStart + IMEM_TEST_SIZE);

			ramAddr &= 0xfffffff8;
			spAddr  &= 0xfffffff8;

			/* 
			 * Now, we configure the length to be 
			 * 	(skip[12], count[8], len[12])
			 */
			/* skip = 8, count = 1 (actually 2), nbytes = 48 */
			skip   = 8;
			count  = 1;
			nbytes = 48;
			length = (skip << 20) | (count << 12) | nbytes;	

			/* If DMA is full, we simply return */
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(SP_STATUS_REG);
#else
			stat = (vu_int)(IO_READ(SP_STATUS_REG));
#endif
			if (stat & SP_STATUS_DMA_FULL) {
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpTestDma",
					dir, spAddr, ramAddr, stat, BUSY_STR);
			} else {
				/* else start DMA and go to next state */
				if (!getSpSemaphore()) {
					fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpTestDma",
					dir, spAddr, ramAddr, length, BUSY_STR);
					break;
				}
				ret = SpTestDma(dir, spAddr, ramAddr, length);
				releaseSpSemaphore();
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpTestDma",
					dir, spAddr, ramAddr, length,
					INSERT_RESULT(ret));
				thread->state = IO_STATE_CHECK_STATUS;
			}
			break;
		}
		case IO_STATE_CHECK_STATUS: {
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(SP_STATUS_REG);
#else
			stat = (vu_int)(IO_READ(SP_STATUS_REG));
#endif
			if (stat != lastStat)
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpDmaStatus",
					SP_STATUS_REG, SP_STATUS_DMA_BUSY, 
					1, stat, DONE_STR);
			lastStat = stat;
			if (!(stat & SP_STATUS_DMA_BUSY)) {
				if (CompareEnabled)
					thread->state = IO_STATE_COMPARE;
				else {
					thread->state = IO_STATE_START;
					thread->inProgress = 0;
				}
			}
			break;
		}
		case IO_STATE_COMPARE: {
			/* Here we compare the 1st word, last word */
			/* nbytes = 48; skip = 8; count = 2
			 * length = skip | count | nbytes;	
			 */
			for (i = 0; i < (count+1); i++) {
				ret = MemSmplCompare(spAddr+(i*nbytes), 
					ramAddr+(i*nbytes)+(i*skip), 
					nbytes/4, 0);
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable,
					"SpDmaCompare", 
					spAddr+(i*nbytes), 
					ramAddr+(i*nbytes)+(i*skip), 
					nbytes/4, 0, INSERT_RESULT(ret));
			}
			thread->state = IO_STATE_INIT;
			thread->inProgress = 0;
			break;
		}
		default: {
                        _TRACE(DERROR,
                        fprintf(LogFp,
                                "\tERROR: Illegal IO state encountered!\n"));
		}
	}  /* switch */

}  /* SpRandDma */

/* Dummy sp test used in vi testing */

void
SpDummyDma(ThreadCmd *thread)
{
	int			i, ret;
	unsigned int		stat;
	static	unsigned int	skip, count, nbytes;
	static	unsigned int	dir      = DIR_TO_RAM;
	static	unsigned int	spAddr   = 0;
	static	unsigned int	ramAddr  = 0;
	static	unsigned int	length	 = IMEM_TEST_SIZE - 16;
	static	unsigned int	lastStat = 0;

	switch (thread->state) {
		case IO_STATE_INIT: 
		case IO_STATE_START: {
			thread->inProgress = 1;

			/* Toggle 
			dir = DIR_TO_RAM;

			spAddr = SP_DMEM_START;

			ramAddr = SpRdramStart + IMEM_TEST_SIZE;

			ramAddr &= 0xfffffff8;
			spAddr  &= 0xfffffff8;

			/* 
			 * Now, we configure the length to be 
			 * 	(skip[12], count[8], len[12])
			 */

			skip   = 0;
			count  = 15;
			nbytes = 256;
			length = (skip << 20) | (count << 12) | nbytes;	

			/* If DMA is full, we simply return */
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(SP_STATUS_REG);
#else
			stat = (vu_int)(IO_READ(SP_STATUS_REG));
#endif
			if (stat & SP_STATUS_DMA_FULL) {
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpTestDma",
					dir, spAddr, ramAddr, stat, BUSY_STR);
			} else {
				/* else start DMA and go to next state */
				if (!getSpSemaphore()) {
					fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpTestDma",
					dir, spAddr, ramAddr, length, BUSY_STR);
					break;
				}
				ret = SpTestDma(dir, spAddr, ramAddr, length);
				releaseSpSemaphore();
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpTestDma",
					dir, spAddr, ramAddr, length,
					INSERT_RESULT(ret));
				thread->state = IO_STATE_CHECK_STATUS;
			}
			break;
		}
		case IO_STATE_CHECK_STATUS: {
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(SP_STATUS_REG);
#else
			stat = (vu_int )(IO_READ(SP_STATUS_REG));
#endif
			if (stat != lastStat)
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpDmaStatus",
					SP_STATUS_REG, SP_STATUS_DMA_BUSY, 
					1, stat, DONE_STR);
			lastStat = stat;
			if (!(stat & SP_STATUS_DMA_BUSY)) {
				thread->state = IO_STATE_INIT;
				thread->inProgress = 0;
				releaseSpSemaphore();
			}
			break;
		}
		default: {
                        _TRACE(DERROR,
                        fprintf(LogFp,
                                "\tERROR: Illegal IO state encountered!\n"));
		}
	}  /* switch */

}  /* SpDummyDma */


/*
 * Use Evan's test to exercise DMA transfers to/from RDRAM from/to D/IMEM
 * Use semaphore to guarantee that only one processor (either SP or CPU)
 * can DMA in/out of D/IMEM. Load Evan's test to D/IMEM and DMA RDRAM data
 * from ROM cartrdige (to 0x0012000 - 0x0012700). 
 *
 * Test uses SP signal 0     : 0 - test not done
 *			       1 - test done
 *              signal [3-1] : test that fails (if all passes, should be 0)
 *
 * Should poll for either the SP halt bit and signal 0 bit to be set
 *
 * Test only uses the upper 2KB in both D/IMEM
 */

void
SpLocDma(ThreadCmd *thread)
{
	unsigned int		stat, data;
	ThreadCmd		*dpThread;
	unsigned int		testFile = 0;
	unsigned int		testNum  = 0;
	static unsigned int	testCount = 1;
	static unsigned int	lastStat = 0;
	static unsigned int	done = 0;
	static unsigned int	init = 0;

	spLocDmaActive = 1;
	switch (thread->state) {
		case IO_STATE_INIT: 
		case IO_STATE_START: {
			thread->inProgress = 1;

			/* 
			 * Assume that D/Imem and Rdram has been pre-loaded
			 * with test data
			 */

#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(SP_STATUS_REG);
#else
			stat = (vu_int )(IO_READ(SP_STATUS_REG));
#endif
			/* Make sure that SP is halted before setting PC */
			if (stat & SP_STATUS_HALT) {
				if (!init) {
					/* Set the SP PC to 0 */
				    if (dma80Enabled) {
#ifdef __sgi__  /* K1--BUG */
					*(vu_int *)PHYS_TO_K1(SP_PC_REG) = 0;
#else
					IO_WRITE(SP_PC_REG, 0);
#endif
					/* This is a hack to fix the problem
					 * with exception handler executing 
					 * the else case
					 */
				        init = 1;
				    }
			            else {	
#ifdef __sgi__  /* K1--BUG */
				        *(vu_int *)PHYS_TO_K1(SP_PC_REG) = 0xb24;
#else
					IO_WRITE(SP_PC_REG, 0xb24);
#endif
				    }
				    init = 1;
				}

				/* Clear halt bit to kick off SP test */
#ifdef __sgi__  /* K1--BUG */
				*(vu_int *)PHYS_TO_K1(SP_STATUS_REG) = 
					SP_CLR_HALT;
#else
				IO_WRITE(SP_STATUS_REG, SP_CLR_HALT);
#endif
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable,
					"SpLocStart", 
					SP_STATUS_REG, 0, testCount, 
					stat, DONE_STR);
				thread->state = IO_STATE_CHECK_STATUS;
			}
			else {
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable,
					"SpLocStart", 
					SP_STATUS_REG, 0, testCount, 
					stat, BUSY_STR);
			}
			break;
		}
		case IO_STATE_CHECK_STATUS: {
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(SP_STATUS_REG);
#else
			stat = (vu_int )(IO_READ(SP_STATUS_REG));
#endif
			if (stat != lastStat)
			    fprintf(LogFp, RTST_MSG_RES2_STR,
				thread - RandThreadTable, "SpLocStatus", 
				SP_STATUS_REG, SP_STATUS_HALT, 
				testCount, stat, DONE_STR);
			lastStat = stat;
			/* Check for halt bit set */
			if (stat & (SP_STATUS_HALT | SP_STATUS_BROKE)) {
			    if (dma80Enabled) {
				/* Check for failed test */
				if (stat & (SP_STATUS_SIG1 | SP_STATUS_SIG2 |
				            SP_STATUS_SIG3)) {
				    fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpLocCheck", 
					SP_STATUS_REG, testCount,
					(SP_STATUS_SIG1 | SP_STATUS_SIG2 | 
					 SP_STATUS_SIG3), stat, FAIL_STR);
        			    errorTotal++;
				} else
				    fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpLocCheck", 
					SP_STATUS_REG, testCount,
					(SP_STATUS_SIG1 | SP_STATUS_SIG2 |
					 SP_STATUS_SIG3), stat, PASS_STR);

				/* Clear broke and signal bits [1-3] */
#ifdef __sgi__  /* K1--BUG */
				*(vu_int *)PHYS_TO_K1(SP_STATUS_REG) = 
					(SP_CLR_BROKE | SP_CLR_SIG1 | 
					 SP_CLR_SIG2 | SP_CLR_SIG3); 
#else
				IO_WRITE(SP_STATUS_REG, SP_CLR_BROKE |
                                      SP_CLR_SIG1 | SP_CLR_SIG2 | SP_CLR_SIG3);
#endif
				/*This is a hack to fix the problem
				 * with exception handler executing 
				 * the else case (branch delay slot issue)
				 */
				init = 1;
			    }
			    else {
				/* Check for failed test */
				if (stat & SP_STATUS_SIG1) {
				    /* Get test file from RDRAM_IMEM_TEST_ID */
#ifdef __sgi__  /* K1--BUG */
				    testFile = *(vu_int *)PHYS_TO_K1(
							RDRAM_IMEM_TEST_ID);
#else
				    testFile = (vu_int )(IO_READ(RDRAM_IMEM_TEST_ID));
#endif
				    testFile = (testFile & 0x000000ff) >> 3;
				    /* Get test number from DMEM address 0 */
				    testNum = IoSpRead(SP_DMEM_START);
				    fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpLocCheck", 
					SP_STATUS_REG, testFile, testNum,
					stat, FAIL_STR);
        			    errorTotal++;
				}
				else {
				    fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "SpLocCheck", 
					SP_STATUS_REG, testCount,
					SP_STATUS_SIG1, stat, PASS_STR);
				}
				/* Clear broke and signal 1 */
#ifdef __sgi__  /* K1--BUG */
				*(vu_int *)PHYS_TO_K1(SP_STATUS_REG) = 
					(SP_CLR_BROKE | SP_CLR_SIG1);
#else
				IO_WRITE(SP_STATUS_REG, SP_CLR_BROKE | SP_CLR_SIG1);
#endif
			    }  /* not dma80 test */

			    thread->state = IO_STATE_START;
			    thread->inProgress = 0;
			    testCount++;
			}
			break;
		}
		default: {
                        _TRACE(DERROR,
                        fprintf(LogFp,
                                "\tERROR: Illegal IO state encountered!\n"));
		}
	}  /* switch */

}  /* SpLocDma */


/***************************************************************************
 * DP thread routines
 */
static void
initDpXbusChannel(unsigned int dmemActive)
{
	/* Setup dmem/rdram-xbus channel */
	if (dmemActive == 0) {
#ifdef __sgi__  /* K1--BUG */
		*(vu_int *)PHYS_TO_K1(DPC_STATUS_REG) = DPC_CLR_XBUS_DMEM_DMA;
#else
		IO_WRITE(DPC_STATUS_REG, DPC_CLR_XBUS_DMEM_DMA);
#endif
		/* This is a hack: without the next statement, program ignores 
		 * the else condition and executes the other memory write: 
		 * could the bug be in the exception handler or compiler?
		 */
		dmemActive = 0;	
	} else {
#ifdef __sgi__  /* K1--BUG */
		*(vu_int *)PHYS_TO_K1(DPC_STATUS_REG) = DPC_SET_XBUS_DMEM_DMA;
#else
		IO_WRITE(DPC_STATUS_REG, DPC_SET_XBUS_DMEM_DMA);
#endif
		dmemActive = 1;

	}

	/* Wait for xbus_dmem_dma set/cleared */
	MemPollStatus(DPC_STATUS_REG, 
		DPC_STATUS_XBUS_DMEM_DMA, (dmemActive != 0) ? 0 : 1, 0);

}  /* initDpXbusChannel */

static void 
parseVerifyInfo(void)
{
	VerifyInfo	*verifp;
	int		count;

	/* Get DP list starting address and length count 
	* count is a multiple of 8 (64-bit)
	*/
#ifdef __sgi__  /* K1--BUG */
	verifp=(VerifyInfo *)(PHYS_TO_K1( VERIFY_INFO_PHYSADDR));
	dplStartAddr = verifp->rdpListAddr;

	/*  
	 * The rdpListSize is 64 bit written back by the SP. The count resides in
	 * the lower 32 bit. Since iosim only traps 32 bit mbus reads, we must
	 * read the lower 32 bit.
	 */  
	count        = *(((unsigned int *)&verifp->rdpListSize)+1);

#else
	{
	   int offset;
           VerifyInfo tmp;

           offset = ((void *) &tmp.rdpListAddr) - ((void *) &tmp);
           dplStartAddr = IO_READ(VERIFY_INFO_PHYSADDR + offset);

           offset = ((void *) &tmp.rdpListSize) - ((void *) &tmp);
           count = IO_READ(VERIFY_INFO_PHYSADDR + offset + 4);

        }
#endif

	/*
	* Calculate DP list ending address and set current address
	*/
	dplEndAddr  = dplStartAddr + count;
	dplCurrAddr = dplStartAddr;

}  /* parseVerifyInfo */


static void
setupRingBuffer(void)
{
	unsigned int	i, data;

	dplRingStartp &= 0xfffffff8;
	initDpXbusChannel(dplRingSource);

	/* Copy from DP list to ring buffer */
	i = 0;
	while ((i < dplRingSize) && 
		(dplCurrAddr < dplEndAddr)) {
#ifdef __sgi__  /* K1--BUG */
		data = *(vu_int *)PHYS_TO_K1(dplCurrAddr);
#else
		data = (vu_int)(IO_READ(dplCurrAddr));
#endif
		if (dplRingSource != FROM_RDRAM) {
			IoSpWrite(dplRingStartp+(i*4), data);
		}
		else
#ifdef __sgi__  /* K1--BUG */
			*(vu_int *)PHYS_TO_K1(dplRingStartp+(i*4)) = data;
#else
			IO_WRITE(dplRingStartp+(i*4), data);
#endif

		dplCurrAddr += 4;
		i++;
	}

	if (dplRingSource == FROM_DMEM2) {	/* Use Evan's test */
		/* Fill remaining space with 0 (noop) */
		while (i < dplRingSize) {
			IoSpWrite(dplRingStartp+(i*4), 0);
			i++;
		}
		/* Set sig0 in SP to tell SP that it can perform
		 * DMA to DPC
		 */
#ifdef __sgi__  /* K1--BUG */
		*(vu_int *)PHYS_TO_K1(SP_STATUS_REG) = SP_SET_SIG0;
#else
		IO_WRITE(SP_STATUS_REG, SP_SET_SIG0);
#endif
		dplRingEndp = Dp2DmemEnd & 0xfffffff8;
	}
	else {
		/* Since ring size is an even number of 32-bit words and
	 	 * start/end addresses are 8-byte aligned, we assume 
	 	 * that "i" (after while loop) is an even number
	 	 */
		dplRingEndp = (dplRingStartp+(i*4)) & 0xfffffff8;

		/* Write start & end addresses */
#ifdef __sgi__  /* K1--BUG */
		*(vu_int *)PHYS_TO_K1(DPC_START_REG) = dplRingStartp;
#else
		IO_WRITE(DPC_START_REG, dplRingStartp);
#endif

		/*
		 * If end is far away from start (at least 10 64-bit 
		 * words, we program 2 end pointers to satisfy the case:
	 	 *	3) start -> end (no stalled) -> end
		 */
		if (((dplRingEndp - dplRingStartp)/8) > 10) {  
#ifdef __sgi__  /* K1--BUG */
			*(vu_int *)PHYS_TO_K1(DPC_END_REG) = dplRingEndp-8;
#else
			IO_WRITE(DPC_END_REG, dplRingEndp-8);
#endif
		}

		/* Reset end pointer */
#ifdef __sgi__  /* K1--BUG */
		*(vu_int *)PHYS_TO_K1(DPC_END_REG) = dplRingEndp;
#else
		IO_WRITE(DPC_END_REG, dplRingEndp);
#endif

	}  /* else */

}  /* setupRingBuffer */


void
DpcRandDma(ThreadCmd *thread)
{
	VerifyInfo 		*verifp;
	int			i, ret;
	unsigned int		stat, data, countAddr;
	unsigned int		spStat;
	static	ThreadCmd	*spThread = NULL;
	static	unsigned int	init      = 0;
	static	unsigned int	count	  = 0;
	static	unsigned int	done	  = 0;
	static	unsigned int	lastStat   = 0;

	/*
	 * For DP testing of the command buffer, we pass it a real display
	 * list for processing. By programming the fifo in circular manner
	 * all the different conditions will be exercised.
	 *	1) idle -> start -> end
	 *	2) start -> end (stalled) -> end
	 *	3) start -> end (no stalled) -> end
	 *	4) start -> end -> wrap
	 *
	 * In this test, we have a DP list and a small ring buffer in RDRAM.
	 * We copy 64-bit words from the DP list to the ring buffer and 
	 * kick off DMA to DP Cmd from the ring buffer. We maintain 2 pointers
	 * (start and end) in the ring buffer. By wrapping these pointers 
	 * around the buffer, we will exercise all the 4 conditions mentioned
	 * above.
	 *               RDRAM
	 *            +-----------+
	 *        +-- |  DP List  |
	 *        |   |           |
	 *        |   |           |
	 *        |   +-----------+
	 *        |   |     .     |
	 *        |   |     .     |
	 *        |   |     .     |
	 *        |   |           |
	 *        |   +-----------+ <- Start
	 *        +-> |  Ring     |
	 *            |  Buffer   | 
	 *	      +-----------+ <- End
	 *
	 * NOTE:
	 *	- Need to enlarge the ring buffer size (to 30 64-bit words)
	 *	so that DMA busy bit can be verified in dmem->xbus direction
	 *	(DP takes around 11 cycles to process CMD FIFO; that is why
	 *	with the current size of 11 64-bit words, we can't see busy
	 *	bit to set)
	 *	- Need to put DpRdramStart at an address such that the RDRAM
	 *	ring buffer spans a 2KB-page boundary.
	 */

	/* Here, we kick off DP for DMA data from RDRAM into DP for
	 * processing and writing out results back to RDRAM
	 * Since RDRAM is mmap with a file, the output can be reviewed
	 * once the test is completed
	 */

	/* For now, we only paint the display list ONCE! */
	if (done) {
		return;
	}
	dpcRandDmaActive = 1;
	switch (thread->state) {
		case IO_STATE_INIT:  
		case IO_STATE_START: {
			thread->inProgress = 1;

			if (!init) {
				init = 1;
				/* Get info from VerifyInfo structure */
				parseVerifyInfo();

				/* Find SpLocDma thread */
				spThread = findActiveThread((void *)SpLocDma);

				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable, "DpcDmaInit",
					dplStartAddr, dplEndAddr, 
					dplEndAddr - dplStartAddr,
					dplRingSize, DONE_STR);
			}  /* if */

			count++;

			/* We alternate between RDRAM and 2 DMEM ring buffers */
			dplRingSource = (dplRingSource == FROM_RDRAM) ?
					FROM_DMEM1 : FROM_RDRAM;

			/* Initialize start pointer and size for ring buffer */
			dplRingStartp = (dplRingSource == FROM_RDRAM) ?
				DpRdramStart : DpDmemStart;
			dplRingStartp &= 0xfffffff8;

			/* 
			 * We randomly pick the ring buffer size to be between 
			 * 4 and 124 32-bit words 
			 */
			dplRingSize = 0;
			while (dplRingSize == 0) {
				dplRingSize = random() & 0x07c;
			}

			/* HACK to use Sp's code to DMA data to CMD FIFO */
			if (dma80Enabled && spThread && 
				((count & 0x3) == 0x3)) {
#ifdef __sgi__  /* K1--BUG */
				data = *(vu_int *)PHYS_TO_K1( SP_STATUS_REG);
#else
				data = (vu_int)(IO_READ( SP_STATUS_REG));
#endif
				if (!(data & SP_STATUS_SIG0)) {
				    dplRingSource = FROM_DMEM2;
				    dplRingStartp = Dp2DmemStart;
				    dplRingSize   = 62; 	/* 248 bytes */
				}
			}

			fprintf(LogFp, RTST_MSG_RES2_STR,
				thread - RandThreadTable, "DpcDmaStart",
				dplRingStartp, dplRingEndp, dplCurrAddr, 
				dplRingSize, "Begin");

			setupRingBuffer();

			/* Read out status */
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(DPC_STATUS_REG);
#else
			stat = (vu_int)(IO_READ(DPC_STATUS_REG));
#endif

			fprintf(LogFp, RTST_MSG_RES2_STR,
				thread - RandThreadTable, "DpcDmaStart",
				dplRingStartp, dplRingEndp, dplCurrAddr, 
				stat, PASS_STR);

			thread->state = IO_STATE_CHECK_STATUS;
			break;
		}
		case IO_STATE_CHECK_STATUS: {
			/* Make sure that Sp's code has acknowledged SIG0 */
			if (dplRingSource == FROM_DMEM2) {
#ifdef __sgi__  /* K1--BUG */
				spStat = *(vu_int *)PHYS_TO_K1(SP_STATUS_REG);
#else
				spStat = (vu_int )(IO_READ(SP_STATUS_REG));
#endif
		        	if (spStat & SP_STATUS_SIG0) {
				    /* We manually start this thread to hopefully
				     * kick off the DMA from ring buffer to DP
				     */
				    SpLocDma(spThread);
				    break;
				}
			}

			/* Wait until DMA counter is at end */
#ifdef __sgi__  /* K1--BUG */
			data = *(vu_int *)PHYS_TO_K1(DPC_CURRENT_REG);
			stat = *(vu_int *)PHYS_TO_K1(DPC_STATUS_REG);
#else
			data = (vu_int )(IO_READ(DPC_CURRENT_REG));
                        stat = (vu_int )(IO_READ(DPC_STATUS_REG));
#endif

			/* Here, we should check for END_VALID */
			if (data == (dplRingEndp & 0x00ffffff)) {
				if (dplCurrAddr >= dplEndAddr)
					thread->state = IO_STATE_COMPARE;
				else
					thread->state = IO_STATE_START;
			}
			fprintf(LogFp, RTST_MSG_RES2_STR,
				thread - RandThreadTable, "DpcDmaCurrent", 
				DPC_CURRENT_REG, data, dplRingEndp,
				stat, DONE_STR);
			break;
		}
		case IO_STATE_COMPARE: {
#ifdef __sgi__  /* K1--BUG */
			stat = *(vu_int *)PHYS_TO_K1(DPC_STATUS_REG);
#else
			stat = (vu_int )(IO_READ(DPC_STATUS_REG));
#endif
			if (stat != lastStat)
				fprintf(LogFp, RTST_MSG_RES2_STR,
					thread - RandThreadTable,
					"DpcDmaStatus", 
					DPC_STATUS_REG, DPC_STATUS_PIPE_BUSY, 
					1, stat, DONE_STR);
			lastStat = stat;
			if (!(stat & DPC_STATUS_PIPE_BUSY)) {
				if (CheckInterrupt(MI_INTR_DP, &stat)) {
					/* Write to bit[11] of MI_INIT_MODE 
					 * to clear interrupt 
					 */
#ifdef __sgi__  /* K1--BUG */
					*(vu_int *)PHYS_TO_K1(
					MI_INIT_MODE_REG) = MI_CLR_DP_INTR;
#else
				 	IO_WRITE(MI_INIT_MODE_REG, MI_CLR_DP_INTR);
#endif

					fprintf(LogFp, RTST_MSG_RES2_STR,
						thread - RandThreadTable,
						"DpcCheckIntr",
						MI_INTR_REG, MI_INTR_DP,
						0, stat, PASS_STR);
				}
				else {
					fprintf(LogFp, RTST_MSG_RES2_STR,
						thread - RandThreadTable,
						"DpcCheckIntr",
						MI_INTR_REG, MI_INTR_DP,
						0, stat, FAIL_STR);
					errorTotal++;
				}

				done = 1;
				thread->state = IO_STATE_INIT;
				thread->inProgress = 0;
			}
			break;
		}
		default: {
                        _TRACE(DERROR,
                        fprintf(LogFp,
                                "\tERROR: Illegal IO state encountered!\n"));
		}
	}  /* switch */
			 
}  /* DpcRandDma */


/***************************************************************************
 * Memory compare by sampling various 32-bit words in the array
 */
int
MemSmplCompare(int src, int dst, int nwords, int failExpected)
{
	/* Compare 'nwords' bytes between source 'src' and destination 'dst' */
	/* 'nwords' must be even and addresses word-aligned */

        int i;
	unsigned int w1, w2;

	errorCount = 0;

	_TRACE(DCOMPARE, fprintf(LogFp,"\tSRC\t\t\t\tDST\n"));

	src &= 0xfffffffc;	/* Ensure addresses are word-aligned */
	dst &= 0xfffffffc;

	/* Here, we sample 1st word, then every 5th word, then last word 
	 * So, if there are 16 words (64-bytes), then it's a diagonal-line
	 * compare
	 */
	for (i = 0; i < nwords; i += 5) {
#ifdef __sgi__  /* K1--BUG */
                w1 = *(vu_int *)PHYS_TO_K1(src+(i*4));
                w2 = *(vu_int *)PHYS_TO_K1(dst+(i*4));
#else
		w1 = (vu_int )(IO_READ(src+(i*4)));
                w2 = (vu_int )(IO_READ(dst+(i*4)));
#endif

		_TRACE(DCOMPARE, fprintf(LogFp, 
			"\t%08x: %08x\t%08x: %08x\t\n",
			src+(i*4), w1, dst+(i*4), w2));

		if (w1 != w2) {
			errorCount++;
                        _TRACE(DERROR, RANDLOG_ERROR(src+(i*4), w1, 
				dst+(i*4), w2));
			break;
		}
	}
	/* Test the last word */
	if (errorCount == 0) {
#ifdef __sgi__  /* K1--BUG */
        	w1 = *(vu_int *)PHYS_TO_K1(src+((nwords-1)*4));
        	w2 = *(vu_int *)PHYS_TO_K1(dst+((nwords-1)*4));
#else
		w1 = (vu_int )(IO_READ(src+((nwords-1)*4)));
		w2 = (vu_int )(IO_READ(dst+((nwords-1)*4)));
#endif

		_TRACE(DCOMPARE, fprintf(LogFp, 
			"\t%08x: %08x\t%08x: %08x\t\n",
			src+((nwords-1)*4), w1, dst+((nwords-1)*4), w2));

		if (w1 != w2) {
			errorCount++;
			_TRACE(DERROR, RANDLOG_ERROR(src+((nwords-1)*4), w1, 
				dst+((nwords-1)*4), w2));
		}
	}

        errorTotal += errorCount;
        return((errorCount == 0) ? 0 : -1);

}  /* MemSmplCompare */


/***************************************************************************
 * Initialize various IO subsystems (RDRAM, PI, AI)
 */
void
IoRandInit(char *testRange) 
{
	
	extern char	IpcName[];
	unsigned int	data = 0;

	fprintf(LogFp, "\n******** Parameters ********\n");
	fprintf(LogFp, "Ipc name                      = %s\n", IpcName);
	fprintf(LogFp, "Debug flag                    = 0x%08x\n", Dflags);
	fprintf(LogFp, "Log file                      = %s\n", LogFile);
	fprintf(LogFp, "Test range                    = %s\n", 
		(testRange == NULL) ? "all" : testRange);
	fprintf(LogFp, "Random test seed              = %d\n", TestSeed);
	fprintf(LogFp, "Minimum run count per thread  = %d\n", MinRunCount);
	fprintf(LogFp, "Minimum iteration for testing = %d\n", LoopCount);
	fprintf(LogFp, "Data comparison               = %s\n", 
		CompareEnabled ? "on" : "off");
	fprintf(LogFp, "Scheduling method             = %s\n", 
		RoundRobinEnabled ? "round-robin" : "random");
	fprintf(LogFp, "Rdram test size               = 0x%08x\n", 
		RdramTestSize);
	fprintf(LogFp, "I/Dmem test size              = 0x%08x\n\n", 
		IMEM_TEST_SIZE);
	fprintf(LogFp, "Rdram size                    = %d\n", RdramSize);

	MiRdramStart = ((RdramSize-1) * (1024*1024)) - (2*RdramTestSize);
	MiRdramEnd   = MiRdramStart + RdramTestSize;
	fprintf(LogFp, "MI:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		MiRdramStart, MiRdramEnd);

	PiRdramStart = ((RdramSize-1) * (1024*1024)) - 1024;
	PiRdramEnd   = PiRdramStart + (5 *1024);
	fprintf(LogFp, "PI:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		PiRdramStart, PiRdramEnd);

	fprintf(LogFp, "  Rom1:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		PiRomStart[0], PiRomEnd[0]);
	fprintf(LogFp, "  Rom2:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		PiRomStart[1], PiRomEnd[1]);
	fprintf(LogFp, "  WRom1:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		PiWRomStart1, PiWRomEnd1);
	fprintf(LogFp, "  WRom2:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		PiWRomStart2, PiWRomEnd2);
	fprintf(LogFp, "SI:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		SiRdramStart, SiRdramEnd);
	fprintf(LogFp, "  Ram:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		SiRamStart, SiRamEnd);
	fprintf(LogFp, "  Rom:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		SiRomStart, SiRomEnd);
	fprintf(LogFp, "AI:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		AiRdramStart, AiRdramEnd);
	fprintf(LogFp, "SP:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		SpRdramStart, SpRdramEnd);
	fprintf(LogFp, "  Imem:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		SpImemStart, SpImemEnd);
	fprintf(LogFp, "  Dmem:\tStart = 0x%08x\tEnd = 0x%08x\n\n", 
		SpDmemStart, SpDmemEnd);
	fprintf(LogFp, "DP:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		DpRdramStart, DpRdramEnd);
	fprintf(LogFp, "  Dmem:\tStart = 0x%08x\tEnd = 0x%08x\n\n", 
		DpDmemStart, DpDmemEnd);
	fprintf(LogFp, "VI:\tStart = 0x%08x\tEnd = 0x%08x\n", 
		ViRdramStart, ViRdramEnd);
	fprintf(LogFp, "\n******** Parameters ********\n\n");

	fprintf(LogFp, "Initializing random environment...\n");

	/* Config RDRAM */
	fprintf(LogFp, RTST_MSG_RES2_STR,
		0, "RdramInit", Rdram1Enabled, RdramSize, 0, 0, DONE_STR);
	RdramInit(RdramSize);

	/* Print out hardware version */
#ifdef __sgi__  /* K1--BUG */
	data = *(vu_int *)PHYS_TO_K1(MI_VERSION_REG);
#else
	data = (vu_int )(IO_READ(MI_VERSION_REG));
#endif
	fprintf(LogFp, "Hardware version = 0x%08x\n", data);

        /* Initialize the Peripheral Interface (PI) controller */
        /* Initial test cause the IO busy bit to always be set? */
	fprintf(LogFp, "Configuring PI Domains...\n");
	fprintf(LogFp, RTST_MSG_RES2_STR,
		0, "PiConfigDomain1", 0x80, 0x20, 0x02, 0x03, DONE_STR);
        PiConfigDomain(PI_DOMAIN1_REG, 0x80, 0x20, 0x02, 0x03);

	fprintf(LogFp, RTST_MSG_RES2_STR,
		0, "PiConfigDomain2", 0x80, 0x20, 0x02, 0x03, DONE_STR);
        PiConfigDomain(PI_DOMAIN2_REG, 0x80, 0x20, 0x02, 0x03);

	/* Init Video Interface (VI) to get proper video clock signal into AI */
	/* t 0102 04400000 00000000 00000000 00000000 */
	fprintf(LogFp, "Initializing VI clock signal...\n");
#ifdef __sgi__  /* K1--BUG */
	*(vu_int *)PHYS_TO_K1(VI_STATUS_REG) = 0;
#else
	IO_WRITE(VI_STATUS_REG, 0);
#endif

	fprintf(LogFp, "Initializing refresh signal...\n");
#ifdef __sgi__  /* K1--BUG */
	*(vu_int *)PHYS_TO_K1(VI_H_SYNC_REG) = 0x130;
#else
	IO_WRITE(VI_H_SYNC_REG, 0x130);
#endif

	/* Config AI: dacRate, bitRate */
	fprintf(LogFp, "Initializing AI...\n");
	/* 
	 * Based on Rambus clock (243.37 MHz) and video clock (48.67 MHz) 
	 * (using cg.v with RAMBUS_CLOCK_PERIOD=4.10897) to get 44.1 KHz 
	 * for audio: DAC rate = 1103 (0x44f), bit rate = 15 (0xf)
	 * For faster sample rate: use DAC rate=0x86, bit rate=0x1
	 */
	if (Ai441Enabled) {
		fprintf(LogFp, RTST_MSG_RES2_STR,
			0, "AiInit", 0x44f, 0x0f, 0x0, 0x0, DONE_STR);
		AiInit(0x44f, 0x0f);	
	}
	else {
		fprintf(LogFp, RTST_MSG_RES2_STR,
			0, "AiInit", 0x86, 0x01, 0x0, 0x0, DONE_STR);
		AiInit(0x86, 0x01);	
	}

	fprintf(LogFp, "Halting SP...\n");
#ifdef __sgi__  /* K1--BUG */
	*(vu_int *)PHYS_TO_K1(SP_STATUS_REG) = SP_SET_HALT;
#else
	IO_WRITE(SP_STATUS_REG, SP_SET_HALT);
#endif

	/* Init D/Imem test area */
	fprintf(LogFp, RTST_MSG_RES2_STR,
		0, "IoSpWrite", SpImemStart, 0x3, 0x0, 0x0, DONE_STR);
	IoSpWrite(SpImemStart, SpImemStart);
	IoSpWrite(SpImemStart+4, SpImemStart+4);
	IoSpWrite(SpImemStart+8, SpImemStart+8);
	IoSpWrite(SpDmemStart, SpDmemStart);
	IoSpWrite(SpDmemStart+4, SpDmemStart+4);
	IoSpWrite(SpDmemStart+8, SpDmemStart+8);

	/* Detect to see which test is loaded in IMEM */
#ifdef __sgi__  /* K1--BUG */
	data = *(vu_int *)PHYS_TO_K1(RDRAM_IMEM_TEST_ID);
#else
	data = (vu_int )(IO_READ(RDRAM_IMEM_TEST_ID));
#endif
	dma80Enabled = ((data & 0xff000000) == 0) ? 1 : 0;
	fprintf(LogFp, "IMEM test dma80 is %s...\n", dma80Enabled ? "on":"off");

	/* Setup all interrupt masks */
	fprintf(LogFp, "Setting all interrupt masks...\n");
#ifdef __sgi__  /* K1--BUG */
	*(vu_int *)PHYS_TO_K1(MI_INTR_MASK_REG) = (MI_INTR_MASK_SET_SP |
		MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI |
		MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI |
		MI_INTR_MASK_SET_DP);
#else
	IO_WRITE(MI_INTR_MASK_REG, (MI_INTR_MASK_SET_SP |
                 MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI |
                 MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI |
                 MI_INTR_MASK_SET_DP));
#endif

#ifdef MANUAL_INIT
	/* Now, we initialize RDRAM with some pattern */
	/* Init 1.5KB in MI space, 3KB in AI, 1KB for SP */

	fprintf(LogFp, "Initializing MI region of RDRAM...\n");
	fprintf(LogFp, RTST_MSG_RES2_STR,
		0, "rdramInit", MiRdramStart, 0x300, 0x0, 0x0, DONE_STR);
	rdramInit(MiRdramStart, 0x300, 0, 0);

	fprintf(LogFp, "Initializing SP regions...\n");
	fprintf(LogFp, RTST_MSG_RES2_STR,
		0, "rdramInit", SpRdramStart, 0x300, 0x0, 0x0, DONE_STR);
	rdramInit(SpRdramStart, 0x300, 0x0000000, 0);

	fprintf(LogFp, "Initializing SI region of RDRAM...\n");
	fprintf(LogFp, RTST_MSG_RES2_STR,
		0, "rdramInit", SiRdramStart, 0x300, 0x0, 0x0, DONE_STR);
	rdramInit(SiRdramStart, 0x300, 0x0000000, 0);

	/* DMA from ROM into RDRAM AI region
	 * The first 1024 bytes in ROM are test data, the next 400 bytes 
	 * are audio data
	 */
	fprintf(LogFp, "DMAing data from ROM to AI region of RDRAM...\n");
	fprintf(LogFp, RTST_MSG_RES2_STR,
		0, "IoPiDmaCopy", DIR_TO_RAM, PI_ROM2_START+1024, AiRdramStart, 
		400, DONE_STR);
	IoPiDmaCopy(DIR_TO_RAM, PI_ROM2_START+1024, AiRdramStart, 400-1);
	fprintf(LogFp, RTST_MSG_RES2_STR,
		0, "MemPollStatus", PI_STATUS_REG, PI_STATUS_DMA_BUSY, 
		1, 0, DONE_STR);
	MemPollStatus(PI_STATUS_REG, PI_STATUS_DMA_BUSY, 1, 0);

	/* DMA from ROM into RDRAM/DP Evan's test region
	 * The first 1024 bytes in ROM are test data, the next 400 bytes 
	 * are audio data, the next 28672 bytes are DP test data
	 */
	fprintf(LogFp, "DMAing data from ROM to DP test region of RDRAM...\n");
	fprintf(LogFp, RTST_MSG_RES2_STR,
		0, "IoPiDmaCopy", DIR_TO_RAM, PI_ROM2_START+1024+400, 
		0x00120000, 0x7000, DONE_STR);
	IoPiDmaCopy(DIR_TO_RAM, PI_ROM2_START+1024+400, 0x00120000, 0x7000-1);

	fprintf(LogFp, RTST_MSG_RES2_STR,
		0, "MemPollStatus", PI_STATUS_REG, PI_STATUS_DMA_BUSY, 
		1, 0, DONE_STR);
	MemPollStatus(PI_STATUS_REG, PI_STATUS_DMA_BUSY, 1, 0);
#endif

	fprintf(LogFp, "Initializing random environment completed!\n");

}  /* IoRandInit */


/***************************************************************************
 * Send command to tell verilog server to shutdown
 */
extern int IoCmd(int, int);

void
ShutdownServer(void)
{
	IoCmd(REQ_QUIT, 0);
}


/***************************************************************************
 * Flush VerifyInfo structure to mmap file
 */
void
FlushVerifyInfo(void)
{
	int		i;
	unsigned int	data;

	/* Read-out/write-in VerifyInfo structure for mmap_rdram to work
	 * with pre-loaded RDRAM
	 */
	for (i=0; i < (sizeof(VerifyInfo)/4) + 2; i++) {
#ifdef __sgi__  /* K1--BUG */
		data = *(vu_int *)PHYS_TO_K1(VERIFY_INFO_PHYSADDR+(i*4));
		*(vu_int *)PHYS_TO_K1(VERIFY_INFO_PHYSADDR+(i*4)) = data;
#else
		data = (vu_int )(IO_READ(VERIFY_INFO_PHYSADDR+(i*4)));
                IO_WRITE(VERIFY_INFO_PHYSADDR+(i*4), data);
#endif
	}

}  /* FlushVerifyInfo */


/***************************************************************************
 * Check to see if interrupt is set in MI interrupt register
 * Return 1 if interrupt is set, 0 otherwise.
 */
int
CheckInterrupt(unsigned int intrBit, unsigned int *stat)
{
	unsigned int ret;

#ifdef __sgi__  /* K1--BUG */
	ret = *(vu_int *)PHYS_TO_K1(MI_INTR_REG);
#else
	ret = (vu_int )(IO_READ(MI_INTR_REG));
#endif
	*stat = ret;
	return(ret & intrBit);

}  /* CheckInterrupt */


/***************************************************************************
 * Unblock and kill all children threads
 * Assume that all threads are not busy and have no outstanding transactions
 */
void
KillAllThreads(void)
{
	int	  i;
	ThreadCmd *thread;

	for (i=0; i < ActiveTableSize; i++) {
                thread = ActiveThreadTable[i];
		_TRACE(DLOG, 
			printf("Unblocking and killing thread %d with pid=%d\n",
				thread - RandThreadTable, thread->pid));

		/* Here, we unblock the thread and kill it */
		/* Do we really need to unblock it first? */
		kill(thread->pid, SIGKILL);
	}

}  /* KillAllThreads */


/***************************************************************************
 * Print all entries in active thread table
 */
void
PrintActiveTable(void)
{
	int 	  i, testCount;
	ThreadCmd *thread;

        _TRACE(DLOG, fprintf(LogFp, 
		"\n*************************************************\n"));
        _TRACE(DLOG, fprintf(LogFp, "Thread Table Status:\n"));

	testCount = 0;
        for (i=0; i < ActiveTableSize; i++) {
                thread = ActiveThreadTable[i];
                _TRACE(DLOG, fprintf(LogFp, THREAD_PRINT_MSG,
			thread - RandThreadTable, thread->pid, thread->entry,
			thread->runCount, thread->busy,
			thread->state, thread->inProgress, thread->name));
		testCount += thread->runCount;
        }

        _TRACE(DLOG, fprintf(LogFp,  
		"\n*************************************************\n"));

        fprintf(LogFp, "\n*************************************************\n");
        fprintf(LogFp,
                "\n\tTotal transactions = %d, total error = %d\n",
		testCount, errorTotal);
        fprintf(LogFp, "\n*************************************************\n");

}  /* PrintRandTable */


/***************************************************************************
 * Find and return a specified thread from the active table
 */
ThreadCmd *
findActiveThread(void *entry)
{
	int i;
	for (i = 0; i < ActiveTableSize; i++) {
		if (ActiveThreadTable[i]->entry == entry)
			return(ActiveThreadTable[i]);
	}
	return(NULL);

}  /* findActiveThread */


/***************************************************************************
 * Add a thread to the active table
 */
void
AddActiveTable(int n)
{
	if (n > RandTableSize-1) {
		fprintf (stderr, "ERROR: test %d out of range\n", n);
		exit(1);
	}
	ActiveTableSize++;
	if (ActiveThreadTable == NULL)
	    ActiveThreadTable = malloc(ActiveTableSize * sizeof(ThreadCmd *));
	else
	    ActiveThreadTable = realloc(ActiveThreadTable,
					ActiveTableSize * sizeof(ThreadCmd *));
	ActiveThreadTable[ActiveTableSize-1] = &RandThreadTable[n];
}


/***************************************************************************
/* Create a mapping array of the active table procedure numbers so implement
/* random round robin
 */
void
initRoundRobin()
{
    int i, ArraySize, Pick, Temp;

    ProcessOrder = (int *) malloc(ActiveTableSize * sizeof(int));
    
    for (i=0; i<ActiveTableSize; i++)
	ProcessOrder[i] = i;

    if (RoundRobinEnabled)
	{

	    ArraySize = ActiveTableSize;
    
	    for (i=0; i<ActiveTableSize-1; i++)
		{
		    Pick = random() % ArraySize;

		    Temp = ProcessOrder[ArraySize-1];
		    ProcessOrder[ArraySize-- -1] = ProcessOrder[Pick];
		    ProcessOrder[Pick] = Temp;
		}    
	}
}

/***************************************************************************
 * Expand a range expression into a table of pointers to active tests
 */
void
rangeExpand(char *range)
{
	char   *exp;
	int     n, state, next_state, start, stop, cindx;

	if (range == NULL) {
		for (n = 0; n < RandTableSize; n++)
			AddActiveTable(n);
		return;
	}

	state = 0;
	start = -1;
	stop = -1;
	cindx = 0;

	for (exp = range; *exp != '\0'; exp++) {
		switch (state) {
		case 0: {
			if (isdigit(*exp)) {
			    start = *exp - '0';
			    next_state = 1;
			} else {
		 	    fprintf (stderr,
			       "Syntax Error: character #%d (%c), state = %d\n",
			       cindx, *exp, state);
			    exit (1);
			}
		      break;
		}
		case 1: {
			if (isdigit(*exp)) {
			    start = (start * 10) + (*exp - '0');
			    next_state = 1;
			} else if (*exp == ',') {
			    AddActiveTable(start);
			    start = -1;
			    next_state = 0;
			} else if (*exp == '-') {
			    next_state = 2;
			} else {
			    fprintf (stderr,
			       "Syntax Error: character #%d (%c), state = %d\n",
			       cindx, *exp, state);
			    exit (1);
			}
			break;
		}
		case 2: {
			if (isdigit(*exp)) {
			    stop = *exp - '0';
			    next_state = 3;
			} else {
			    fprintf (stderr,
			       "Syntax Error: character #%d (%c), state = %d\n",
			       cindx, *exp, state);
			    exit (1);
			}
			break;
		}
		case 3: {
			if (isdigit(*exp)) {
			    stop = (stop * 10) + (*exp - '0');
			    next_state = 3;
			} else if (*exp == ',') {
			    if (start >= stop) {
				fprintf (stderr,
				"Syntax Error: in range first number(%d) must be smaller than second(%d)\n",
					start, stop);
				exit (1);
			    }
			    for (n = start; n <= stop; n++)
				AddActiveTable(n);
			    start = stop = -1;
			    next_state = 0;
			} else {
			    fprintf (stderr,
			       "Syntax Error: character #%d (%c), state = %d\n",
			       cindx, *exp, state);
			    exit (1);
			}
			break;
		}
		}
		state = next_state;
		cindx++;
	}

	/*
	 *  Cleanup
	 */

	if (start != -1) {
		if (stop == -1) {
		    AddActiveTable(start);
		} else {
		    if (start >= stop) {
			fprintf (stderr,
				"Syntax Error: in range first number(%d) must be smaller than second(%d)\n",
				start, stop);
			exit (1);
		    }
		    for (n = start; n <= stop; n++)
			AddActiveTable(n);
		}
	}

}  /* rangeExpand */