si.tst
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//****************************************************************************
//
// File: si.tst
// Test file for Serial Interface (SI)
//
// $Revision: 1.1.1.1 $
//
// File Format:
//
// t <id> <arg1> <arg2> <arg3> <arg4> - Run test id with the 4 args
// where id = decimal number
// argX = hex number
// q - Quit testing and shutdown verilog
// server
//
//
//****************************************************************************
//****************************************************************************
// Configure RDRAM
t 0000 00000000 00000000 00000000 00000000
// Init RDRAM with pattern data (rdram_addr, nbytes, pattern_key)
t 0013 00000000 00000080 81234567 00000000
//****************************************************************************
// W/R data into SI DRAM address reg -> SHOULD PASS
// HW resets the data to be word-aligned with upper 2 bytes zeroed out
// Test SI DRAM Address Reg: address, data
t 0103 04800000 00000012 00000010 00000000
t 0103 04800000 00000124 00000124 00000000
t 0103 04800000 00001246 00001244 00000000
t 0103 04800000 00012468 00012468 00000000
t 0103 04800000 0012468C 0012468C 00000000
t 0103 04800000 012468C0 002468C0 00000000
//****************************************************************************
// Read pre-loaded data from PIF and compare -> SHOULD PASS
// (assuming pre-loaded data contains data = (address >> 2) & 0x0000FFFF)
// Test SI IO RD: address, data to compare
t 0101 1fc00000 00000000 00000000 00000000
t 0101 1fc00004 00000001 00000000 00000000
t 0101 1fc00008 00000002 00000000 00000000
t 0101 1fc007bc 000001ef 00000000 00000000
t 0101 1fc007c0 000001f0 00000000 00000000
t 0101 1fc007c4 000001f1 00000000 00000000
t 0101 1fc007c8 000001f2 00000000 00000000
//****************************************************************************
// Test SI DMA: type (1=RD4B, 2=WR4B, 3=RD64B, 4=WR64B),
// pif_address, dram_address
//****************************************************************************
// IO Read 4 Bytes PIF -> DRAM (on word-aligned) -> SHOULD PASS
t 0031 1fc007c0 000001f0 00000000 00000000
t 0031 1fc00004 00000001 00000000 00000000
//****************************************************************************
// Io Write/Read 4 Bytes PIF <- DRAM -> SHOULD PASS
t 0032 1fc007cc 12345678 00000000 00000000
// Interrupt should be set due to IO write - test for interrupt bit
t 0104 04800018 00001000 00000000 00000000
// Reset interrupt by writing into status reg
t 0102 04800018 00000000 00000000 00000000
// Now, test for interrupt bit to be reset
t 0104 04800018 00001000 00000001 00000000
t 0032 1fc007d0 89abcdef 00000000 00000000
t 0032 1fc007d4 12344321 00000000 00000000
t 0032 1fc007d8 fedcba98 00000000 00000000
//****************************************************************************
// Here, we reset interrupt by writing into status register
// Interrupt should be set due to previous IO write
t 0102 04800018 00000000 00000000 00000000
//****************************************************************************
// DMA 64 Bytes from PIF to DRAM (on 8B-aligned) -> SHOULD PASS
t 0033 00000003 1fc007c0 00000008 00000000
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now, test for interrupt bit
t 0104 04800018 00001000 00000000 00000000
// Reset interrupt bit
t 0102 04800018 00000000 00000000 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 1fc007c0 00000008 00000040 00000000
//****************************************************************************
// DMA 64 Bytes from PIF to DRAM (on 8B-aligned) -> SHOULD PASS
// since SW reset address to be word-aligned (&0xfffffffc)
t 0033 00000003 1fc007c0 00000010 00000000
// Now, test for DMA (error & busy bits)
t 0104 04800018 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 1fc007c0 00000010 00000040 00000000
//****************************************************************************
// DMA 64 Bytes from DRAM to PIF (not on 8B-aligned) -> SHOULD FAIL
t 0033 00000003 1fc007c0 00000004 00000000
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 1fc007c0 00000004 00000040 00000001
//****************************************************************************
// DMA 64 Bytes from DRAM to PIF (on 8B-aligned) -> SHOULD PASS
t 0033 00000004 1fc007c0 00000040 00000000
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 1fc007c0 00000040 00000040 00000000
//****************************************************************************
// DMA 64 Bytes from DRAM to PIF and issue IO read -> DMA SHOULD FAIL
t 0033 00000004 1fc007c0 00000000 00000000
// Now, issue an IO read to reset vector+4 without waiting for DMA completion
//t 0031 1fc00004 00000001 00000000 00000000
t 0101 1fc00004 00000001 00000000 00000000
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 1fc007c0 00000000 00000040 00000001
//****************************************************************************
// Issue an IO read and start DMA 64B from DRAM to PIF -> SHOULD PASS
// First, issue an IO read to reset vector+8 without waiting for DMA completion
t 0101 1fc00008 00000002 00000000 00000000
// 64B xfer PIF <- DRAM (Note: addresses must be 64B-aligned)
t 0033 00000004 1fc007c0 00000040 00000000
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 1fc007c0 00000040 00000040 00000000
//****************************************************************************
// 64B xfer PIF <- DRAM (Note: addresses must be 8B-aligned) -> SHOULD PASS
t 0033 00000004 1fc007c0 00000000 00000000
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 1fc007c0 00000000 00000040 00000000
//****************************************************************************
// Issue 2 IO reads back-to-back -> SHOULD PASS
// read from PIF ROM area
t 0101 1fc00010 00000004 00000000 00000000
t 0101 1fc00038 0000000e 00000000 00000000
//****************************************************************************
// DMA 64B from PIF -> DRAM npages -> SHOULD PASS
// 4B xfer PIF -> DRAM (dma_type, pif_address, dram_address, npages)
t 0037 00000003 1fc007c0 00000000 00000005
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 1fc007c0 00000000 00000040 00000000
t 0105 1fc007c0 00000800 00000040 00000000
t 0105 1fc007c0 00001000 00000040 00000000
t 0105 1fc007c0 00001800 00000040 00000000
t 0105 1fc007c0 00002000 00000040 00000000
//****************************************************************************
// Issue 2 DMAs back-to-back: (1) 64B PIF -> DRAM, (2) 64B DRAM -> PIF -> FAIL
t 0033 00000003 1fc007c0 00000100 00000000
// Now, issue another DMA 64B xfer PIF <- DRAM
t 0033 00000004 1fc007e0 00000008 00000000
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
// First DMA might pass, 2nd DMA should fail
t 0105 1fc007c0 00000100 00000040 00000000
t 0105 1fc007e0 00000008 00000040 00000001
//****************************************************************************
// Issue 2 DMAs back-to-back: (1) 64B PIF -> DRAM, (2) IO WR -> PIF -> FAIL
t 0033 00000003 1fc007c0 00000010 00000000
// Now, issue an IO Write -> PIF (Failed?)
t 0032 1fc007d0 12345678 00000000 00000001
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
// First DMA might pass
t 0105 1fc007c0 00000010 00000040 00000000
//****************************************************************************
// Issue 2 DMAs back-to-back: (1) 64B PIF -> DRAM, (2) 64B PIF -> DRAM -> FAIL
t 0033 00000003 1fc007c0 00000020 00000000
// Now, issue another DMA 64B xfer PIF -> DRAM
t 0033 00000003 1fc007d0 00000060 00000000
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
// First DMA might pass, 2nd DMA should fail
t 0105 1fc007c0 00000020 00000040 00000000
t 0105 1fc007d0 00000060 00000040 00000001
//****************************************************************************
// Dump PIF RAM: address, nwords
t 0106 1fc007bc 00000012 00000000 00000000
t 0106 1fc00000 00000012 00000000 00000000
//****************************************************************************
// QUIT
//****************************************************************************
q