bootstrap.s
1.99 KB
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/*
* Copyright 1996, Silicon Graphics, Inc.
* ALL RIGHTS RESERVED
*
* UNPUBLISHED -- Rights reserved under the copyright laws of the United
* States. Use of a copyright notice is precautionary only and does not
* imply publication or disclosure.
*
* U.S. GOVERNMENT RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in FAR 52.227.19(c)(2) or subparagraph (c)(1)(ii) of the Rights
* in Technical Data and Computer Software clause at DFARS 252.227-7013 and/or
* in similar or successor clauses in the FAR, or the DOD or NASA FAR
* Supplement. Contractor/manufacturer is Silicon Graphics, Inc.,
* 2011 N. Shoreline Blvd. Mountain View, CA 94039-7311.
*
* THE CONTENT OF THIS WORK CONTAINS CONFIDENTIAL AND PROPRIETARY
* INFORMATION OF SILICON GRAPHICS, INC. ANY DUPLICATION, MODIFICATION,
* DISTRIBUTION, OR DISCLOSURE IN ANY FORM, IN WHOLE, OR IN PART, IS STRICTLY
* PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF SILICON
* GRAPHICS, INC.
*
*/
#include "regdef.h"
#include "asm.h"
#include <R4300.h>
#include <rcp.h>
/*
* Final stage of IPL4 bootstrap procedure
*/
LEAF(FinalBoot)
# invalidate the icache
la t0,K0BASE
addu t1,t0,ICACHE_SIZE
subu t1,ICACHE_LINESIZE
.set noreorder
mtc0 zero,C0_TAGLO
mtc0 zero,C0_TAGHI
inval_icache:
cache CACH_PI|C_IST,0(t0) # use index invalidate
bltu t0,t1,inval_icache # on entire cache
addu t0,ICACHE_LINESIZE
.set reorder
# writeback invalidate the dcache
li t0,K0BASE
li t2,DCACHE_SIZE
addu t1,t0,t2
subu t1,DCACHE_LINESIZE
inval_dcache:
.set noreorder
cache CACH_PD|C_IWBINV,0(t0) # Use index writeback invalidate
bltu t0,t1,inval_dcache # on entire primary cache
addu t0,DCACHE_LINESIZE
.set reorder
jr a0 # no deposit no return
nop
END(FinalBoot)