rmonrcp.s
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/*
* ==========================================================================
* Copyright (c) 1994, Silicon Graphics, Inc. All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied
* or duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc. handleSelectExceptions
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished
* rights reserved under the Copyright Laws of the United States.
* ==========================================================================
*/
#include <regdef.h>
#include <asm.h>
#include <rcp.h>
.ent __rmonRCPrunning 2
.globl __rmonRCPrunning
__rmonRCPrunning:
#if defined( _EMULATOR )
subu sp, 24
sw ra, 20(sp)
li a0, SP_STATUS_REG
addu a1, sp, 16
jal __osSpRawReadIo
lw v0, 16(sp)
lw ra, 20(sp)
addu sp, 24
move t0, v0
move v0, zero /* assume not */
#else
move v0, zero /* assume not */
lw t0, PHYS_TO_K1(SP_STATUS_REG)
#endif
andi t0, t0, (SP_STATUS_HALT | SP_STATUS_BROKE)
bne t0, zero, isHalted
ori v0, v0, 1
isHalted:
j ra
.end __rmonRCPrunning
.ent __rmonIdleRCP
.globl __rmonIdleRCP
__rmonIdleRCP:
#if defined( _EMULATOR )
subu sp, 24
sw ra, 20(sp)
wait4dma:
li a0, SP_DMA_BUSY_REG
addu a1, sp, 16
jal __osSpRawReadIo
lw v0, 16(sp)
#else
li a0, PHYS_TO_K1(SP_DMA_BUSY_REG)
wait4dma:
lw v0, 0(a0)
#endif
bne v0, zero, wait4dma
li a1, (SP_CLR_INTR_BREAK | SP_SET_HALT)
#if defined( _EMULATOR )
li a0, SP_STATUS_REG /* status reg */
jal __osSpRawWriteIo
#else
li a0,PHYS_TO_K1(SP_STATUS_REG)
sw a1, 0(a0) /* issue it */
#endif
awaitIdle:
#if defined( _EMULATOR )
li a0, SP_STATUS_REG /* status reg */
addu a1, sp, 16
jal __osSpRawReadIo
lw v0, 16(sp)
#else
li a0, PHYS_TO_K1(SP_STATUS_REG) /* status reg */
lw v0, 0(a0)
#endif
andi v0, (SP_STATUS_HALT | SP_STATUS_BROKE)
beq v0, 0, awaitIdle
#if defined( _EMULATOR )
lw ra, 20(sp)
addu sp, 24
#endif
j ra
.end __rmonIdleRCP
.ent __rmonStepRCP
.globl __rmonStepRCP
__rmonStepRCP:
#if defined( _EMULATOR )
subu sp, 24
sw ra, 20(sp)
li a0, SP_STATUS_REG /* status reg */
li a1, (SP_CLR_HALT | SP_CLR_BROKE | SP_SET_SSTEP | SP_CLR_INTR_BREAK)
jal __osSpRawWriteIo
#else
li a0, PHYS_TO_K1(SP_STATUS_REG) /* status reg */
li a1, (SP_CLR_HALT | SP_CLR_BROKE | SP_SET_SSTEP | SP_CLR_INTR_BREAK)
sw a1, 0(a0) /* issue it */
#endif
b awaitIdle
.end __rmonStepRCP
.ent __rmonRunRCP 2
.globl __rmonRunRCP
__rmonRunRCP:
#if defined( _EMULATOR )
subu sp, 16
sw ra, 16(sp)
li a0, MI_INTR_MASK_REG
li a1, 2 /* set sp int mask (allow break int) */
jal __osSpRawWriteIo
li a0, SP_STATUS_REG /* cmd/status reg */
li a1, 0x10025 /* clears step halt and break bits,
sets interrupt on break */
jal __osSpRawWriteIo
lw ra, 16(sp)
addu sp, 16
#else
li a0, PHYS_TO_K1(MI_INTR_MASK_REG)
li a1, 2 /* set sp int mask (allow break int) */
sw a1, 0(a0) /* issue it */
li a0, PHYS_TO_K1(SP_STATUS_REG)
li a1, (SP_SET_INTR_BREAK | SP_CLR_SSTEP | SP_CLR_BROKE | SP_CLR_HALT)
sw a1, 0(a0) /* issue it */
#endif
j ra
.end __rmonRunRCP