/*====================================================================
 * pirawdma.c
 *
 * Copyright 1995, Silicon Graphics, Inc.
 * All Rights Reserved.
 *
 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics,
 * Inc.; the contents of this file may not be disclosed to third
 * parties, copied or duplicated in any form, in whole or in part,
 * without the prior written permission of Silicon Graphics, Inc.
 *
 * RESTRICTED RIGHTS LEGEND:
 * Use, duplication or disclosure by the Government is subject to
 * restrictions as set forth in subdivision (c)(1)(ii) of the Rights
 * in Technical Data and Computer Software clause at DFARS
 * 252.227-7013, and/or in similar or successor clauses in the FAR,
 * DOD or NASA FAR Supplement. Unpublished - rights reserved under the
 * Copyright Laws of the United States.
 *====================================================================*/

/**************************************************************************
 *
 *  $Revision: 1.1.1.2 $
 *  $Date: 2002/10/29 08:06:43 $
 *  $Source: /root/leakn64/depot/rf/sw/n64os20l/libultra/nintendo/pi/pirawdma.c,v $
 *
 **************************************************************************/

#include "osint.h"
#include "rcp.h"
#include "assert.h"


/*
 * Name:   __osPiRawStartDma
 *
 * Description:
 *	Based on the input direction (OS_READ or OS_WRITE), setup a DMA 
 *	transfer between RDRAM and PI device address space.
 *	devAddr and dramAddr specifies the DMA buffer address of the device
 *	memory and RDRAM, respectively. size contains the number of bytes to 
 *	transfer. Note that the ROM address needs to be 16-bit aligned and
 *	RDRAM address 64-bit aligned. Furthermore, the size must be a
 *	multiple of 2 bytes. Maximum transfer size is 16 MBytes (24-bit).
 *	If the interface is busy, return a "-1" and abort the operation.
 *
 * Globals Referenced: 
 *	None
 */
s32
__osPiRawStartDma(s32 direction, u32 devAddr, void *dramAddr, u32 size)
{
    register u32 stat;

#ifdef _DEBUG
    /* Check for valid direction */
    if ((direction != OS_READ) && (direction != OS_WRITE)) {
	__osError(ERR_OSPIRAWSTARTDMA_DIR, 1, direction);
	return(-1);
    }

    /* Need 16-bit alignment for ROM */
    if (devAddr & 0x1) {
	__osError(ERR_OSPIRAWSTARTDMA_DEVADDR, 1, devAddr);
	return(-1);
    }

    /* Need 64-bit alignment for RDRAM */
    if ((u32)dramAddr & 0x7) {
	__osError(ERR_OSPIRAWSTARTDMA_ADDR, 1, dramAddr);
	return(-1);
    }

    /* Size must be a multiple of 2 bytes */
    if (size & 0x1) {
	__osError(ERR_OSPIRAWSTARTDMA_SIZE, 1, size);
	return(-1);
    }

    /* Check for valid range: 0 < size <= 16 MBytes */
    if ((size == 0) || (size > (16*1024*1024))) {
	__osError(ERR_OSPIRAWSTARTDMA_RANGE, 1, size);
	return(-1);
    }
#endif

    stat = IO_READ(PI_STATUS_REG);
    while (stat & (PI_STATUS_IO_BUSY | PI_STATUS_DMA_BUSY)) {
        stat = IO_READ(PI_STATUS_REG);
    } 

    IO_WRITE(PI_DRAM_ADDR_REG, osVirtualToPhysical(dramAddr));
    IO_WRITE(PI_CART_ADDR_REG, K1_TO_PHYS((u32)osRomBase | devAddr));

    /* Note that actual programmed size of transfer = size - 1 */
    switch (direction) {
        case OS_READ: {				/* PI -> RDRAM */
            IO_WRITE(PI_WR_LEN_REG, size-1);
            break;
        }
        case OS_WRITE: {			/* PI <- RDRAM */
            IO_WRITE(PI_RD_LEN_REG, size-1);
            break;
        }
        default: {
            return(-1);
        }
    }

    return(0);

}  /* __osPiRawStartDma */