.TH osInvalDCache 3P local "Silicon Graphics, Inc."
.SH NAME
.upperok
osInvalDCache \- invalidate CPU data cache lines
.SH SYNOPSIS
.nf
\f3
.Op c
#include <ultra64.h>
.sp .8v
void osInvalDCache(void \(**vaddr, s32 nbytes);
.Op
\f1
.fi
.SH DESCRIPTION
The MIPS R4300 CPU implements a 8 kilobyte direct mapped data cache
with a line size of 16 bytes.
The cache is not coherent with respect to physical memory and
thus cache lines must be explicitly invalidated when it is desired that
stale data not be used when more recent data exists in physical
memory.
The
.I osInvalDCache
call invalidates all data cache lines that contain the region
.IR  "[vaddr, vaddr + nbytes)" .
The given address
.I vaddr
must be a CPU virtual address,
either direct mapped or mapped via the CPU TLB.
If
.I vaddr
is not aligned to the a cache line boundary,
and
.I nbytes
is not a multiple of the cache line size,
a slightly larger region may be invalidated.
.PP
This routine is most commonly used in the situation where newer program
data is to be copied to physical memory
from a direct memory access device (DMA)
at address locations that have been previously been read or written by
the CPU.
In this case, the cached data is out of data with respect to physical memory,
and thus cache lines associated with these addresses must be invalidated
prior to accessing these data locations.
.SH "SEE ALSO"
.IR osMapTLB (3P),
.IR osInvalICache (3P),
.IR osWritebackDCache (3P)