osPiRawStartDma.3p
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.TH osPiRawStartDma 3P local "Silicon Graphics, Inc."
.SH NAME
.upperok
osPiRawStartDma, osPiRawWriteIo, osPiRawReadIo, osPiGetStatus \-
unmanaged access to the parallel interface (PI)
.SH SYNOPSIS
.nf
\f3
.Op c
#include <ultra64.h>
.sp .8v
s32 osPiRawStartDma(s32 direction, u32 devAddr, void \(**vAddr,
u32 nbytes);
.sp .8v
s32 osPiRawWriteIo(u32 devAddr, u32 data);
.sp .8v
s32 osPiRawReadIo(u32 devAddr, u32 \(**data);
.sp .8v
u32 osPiGetStatus(void);
.Op
\f1
.fi
.SH DESCRIPTION
The parallel interface (PI) is responsible for the transport of data between
RDRAM and bulk-storage devices (BSD) which could be ROM, RAM, CDROM, and other
technologies.
These functions listed above provide low level access to the PI.
These functions should only be used when it is ensured that there is no
other services accessing the PI. For this reason,
it is recommended that "cooked" or managed PI access routines be used
for most purposes;
see
.IR osPiStartDma (3P)
for details on this functionality.
The raw routines may be useful, however, immediately after the application
boot procedure is entered and before the operating system is initialized.
Based on the input
.I direction
(OS_READ or OS_WRITE),
.I osPiRawStartDma
sets up a DMA transfer between RDRAM virtual address
.I vAddr
and PI device address
.I devAddr.
The length count
.I nbytes
contains the number of bytes to transfer (up to 16 Mbytes) and must be a
multiple of 2 bytes.
The PI device address
.I devAddr
must be 2-byte aligned.
The RDRAM virtual address
.I vAddr
must be \fIat least \fR 8-byte aligned,
but for OS_READ DMA operations, a stricter alignment is recommended.
See
.IR OS_DCACHE_ROUNDUP_ADDR (3P)
for a description of the problems that may result when transfers
are not an integral number of cache lines.
The
.I osPiRawStartDma
routine also polls the interface for idleness
before programming the DMA registers.
.PP
The
.I osPiRawWriteIo
routine performs a 32-bit programmed IO write to the PI device address
.I devAddr.
It polls the interface for idleness before performs the operation.
Similarly,
.I osPiRawReadIo
performs a 32-bit programmed IO read from the PI device address
.I devAddr
and returns the value in
.I data.
It also polls the interface for idleness before performs the operation.
Note that the device address
.I devAddr
must be 2-byte aligned.
.PP
.I osPiGetStatus
simply returns the hardware status of PI.
The 32-bit returned value contains the following bit patterns:
.TP 10
.I PI_STATUS_IO_BUSY
A previously issued programmed IO request has not yet completed.
.TP
.I PI_STATUS_DMA_BUSY
A previously issued DMA request has not yet completed.
.TP
.I PI_STATUS_ERROR
An IO request was issued while DMA was busy.
.PP
The
.I osPiGetStatus
routine will most likely be used to ensure that the last of a string of
raw IO requests has completed.
.PP
.SH SEE ALSO
.IR osPiStartDma (3P)