module rdp_vms_clock(clk, gclk, reset_l, o_clk, o_gclk, o_reset_l);

input clk;
input gclk;
input reset_l;
output o_clk;
output o_gclk;
output o_reset_l;
integer rdram_ready;
initial rdram_ready = 1;

initial begin

    wait (reset_l);
    wait (!reset_l);
    wait (reset_l);
    @(posedge clk);

    reality.r4200b_0.test_selected <= 1'b1;
    rdram_ready = 0;
    reality.r4200b_0.config_rdram;
    rdram_ready = 1;

end
    
    assign o_clk = (rdram_ready == 0 ? 1'b0 : clk);
    assign o_gclk = (rdram_ready == 0 ? 1'b0 : gclk);
    assign o_reset_l = (reset_l === 1'bx ? 1'b0 : reset_l);

endmodule