tm.h
6.08 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
/*
* Texture Memory stuff
*
*
*/
#ifndef TMEM_INCLD
#define TMEM_INCLD
#include "ints.h"
/*
* Mode Word Texel Size Decode
*/
typedef enum {
TC_4BIT,
TC_8BIT,
TC_16BIT,
TC_32BIT
} TcMwSizes;
/*
* Mode Word Texel Type Decode
*/
typedef enum {
TC_RGBA,
TC_YUV,
TC_CI,
TC_IA,
TC_I
} TcMwTypes;
/*
* Texture Lookup Table Type decode
*/
typedef enum {
TC_TLUT_RGBA_16b,
TC_TLUT_IA_16b
} TcTlutType;
/*
* Texture Memory Structure
*/
typedef struct tmem
{
/* R e q u i r e d by C-sim */
char *label; /* instance name */
char **argv; /* command line args */
int argc; /* command line args count */
int gclk; /* gated clock */
int gclk_old; /* gated clock */
int copy_load_e; /* enable signal for bidirectional bus */
/* I n p u t signals */
int adrs_bnk0l; /* clock 7, address to low bank 0 */
int adrs_bnk1l; /* clock 7, address to low bank 1 */
int adrs_bnk2l; /* clock 7, address to low bank 2 */
int adrs_bnk3l; /* clock 7, address to low bank 3 */
int adrs_bnk0h; /* clock 7, address to high bank 0 */
int adrs_bnk1h; /* clock 7, address to high bank 1 */
int adrs_bnk2h; /* clock 7, address to high bank 2 */
int adrs_bnk3h; /* clock 7, address to high bank 3 */
int adrs_a; /* clock 8, address <12>,<3:0> */
int adrs_b_ba; /* clock 8, address <12>,<3:0> */
int adrs_c; /* clock 8, address <12>,<3:0> */
int adrs_d_ba; /* clock 8, address <12>,<3:0> */
int adrs_b_rg; /* clock 8, address <12>,<3:0> */
int adrs_d_rg; /* clock 8, address <12>,<3:0> */
int swap_rg; /* clock 8, flag, reverse texel order */
int swap_ba; /* clock 8, flag, reverse texel order */
int tlut_en; /* clock 6, enable texture lookup table */
int tlut_en_d1; /* clock 7, delayed tlut_en */
int tlut_en_d2; /* clock 8, delayed tlut_en */
int tlut_type; /* clock 8, texture lookup table type */
int tile_tex_type; /* clock 6, 3-bit type field */
int tile_tex_size; /* clock 6, 2-bit size field */
int palette; /* clock 7, 4-bit palette number for CI mode */
int palette_1d; /* clock 8, 4-bit palette number for CI mode */
int load_dv; /* data valid for texture load bus */
unsigned int odd_t; /* clock 6, odd line */
unsigned int a_three; /* clock 6, 3rd bit of address of texel a */
unsigned int a_twelve; /* clock 6, 12th bit of address of texel a */
unsigned int copy; /* clock 6 */
int reset_l;
int iddq;
int bist_go;
int bist_check;
/* O u t p u t S i g n a l s */
int red_a; /* clock 9, s,8.0 */
int green_a; /* clock 9, s,8.0 */
int blue_a; /* clock 9, s,8.0 */
int alpha_a; /* clock 9, s,8.0 */
int red_b; /* clock 9, s,8.0 */
int green_b; /* clock 9, s,8.0 */
int blue_b; /* clock 9, s,8.0 */
int alpha_b; /* clock 9, s,8.0 */
int red_c; /* clock 9, s,8.0 */
int green_c; /* clock 9, s,8.0 */
int blue_c; /* clock 9, s,8.0 */
int alpha_c; /* clock 9, s,8.0 */
int red_d; /* clock 9, s,8.0 */
int green_d; /* clock 9, s,8.0 */
int blue_d; /* clock 9, s,8.0 */
int alpha_d; /* clock 9, s,8.0 */
int clr_ind_a; /* clock 8, <7:0> */
int clr_ind_b; /* clock 8, <7:0> */
int clr_ind_c; /* clock 8, <7:0> */
int clr_ind_d; /* clock 8, <7:0> */
int64 copy_load; /* copy load <63:0>, how to handle this signal? */
int64 copy_load2; /* copy load <63:0>, how to handle this signal? */
int vm_out; /* dereferenced pixel to VM */
/* I n t e r m e d i a t e S i g n a l s */
unsigned int swap_a_lo: 5; /* clock 8, swapped address bits <12>,<3:0> */
unsigned int swap_b_lo: 5; /* clock 8, swapped address bits <12>,<3:0> */
unsigned int swap_c_lo: 5; /* clock 8, swapped address bits <12>,<3:0> */
unsigned int swap_d_lo: 5; /* clock 8, swapped address bits <12>,<3:0> */
unsigned int swap_a_hi: 5; /* clock 8, swapped address bits <12>,<3:0> */
unsigned int swap_b_hi: 5; /* clock 8, swapped address bits <12>,<3:0> */
unsigned int swap_c_hi: 5; /* clock 8, swapped address bits <12>,<3:0> */
unsigned int swap_d_hi: 5; /* clock 8, swapped address bits <12>,<3:0> */
unsigned int texL0: 16; /* clock 8, texel from low bank 0 */
unsigned int texL1: 16; /* clock 8, texel from low bank 1 */
unsigned int texL2: 16; /* clock 8, texel from low bank 2 */
unsigned int texL3: 16; /* clock 8, texel from low bank 3 */
unsigned int texH0: 16; /* clock 8, texel from high bank 0 */
unsigned int texH1: 16; /* clock 8, texel from high bank 1 */
unsigned int texH2: 16; /* clock 8, texel from high bank 2 */
unsigned int texH3: 16; /* clock 8, texel from high bank 3 */
unsigned int adrs_a_d1: 5; /* clock 8, delay <12>,<3:0> */
unsigned int adrs_b_ba_d1: 5; /* clock 8, delay <12>,<3:0> */
unsigned int adrs_c_d1: 5; /* clock 8, delay <12>,<3:0> */
unsigned int adrs_d_ba_d1: 5; /* clock 8, delay <12>,<3:0> */
unsigned int adrs_b_rg_d1: 5; /* clock 8, delay <12>,<3:0> */
unsigned int adrs_d_rg_d1: 5; /* clock 8, delay <12>,<3:0> */
int64 di_high; /* clock 8 */
int64 di_low; /* clock 8 */
unsigned int we01_low: 1; /* clock 7 */
unsigned int we23_low: 1; /* clock 7 */
unsigned int we01_high: 1; /* clock 7 */
unsigned int we23_high: 1; /* clock 7 */
int64 copy_load_d1; /* clock 7 */
int tile_tex_type_d1; /* clock 7 */
int tile_tex_type_d2; /* clock 8 */
int tile_tex_size_d1; /* clock 7 */
int tile_tex_size_d2; /* clock 8 */
unsigned int tmem_type: 2; /* clock 7 */
} tm_t;
/*
* P r o t o t y p e s
*/
void tm(tm_t **pp0, tm_t **pp1);
void tm_init(tm_t *p0, tm_t *p1);
void load_tmem(char *file);
void dump_tmem(char *file);
#endif /* TMEM_INCLD */