do_sim
4.55 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
#!/bin/csh -f
#
# Shell script for generating tabular trace file
#
# Usage: do_sim <test>
#
# 12/20/94 TD
#
if ( $#argv != 1 ) then
echo "Usage: $0 <test>"
exit
endif
vlsishell << EOF
set echo on
####################################
# invoke qsim and load netlist
####################################
qsim
mode compassqsim
load [nls]ms
####################################
# setup environment
####################################
radix 16
options bidirConflict
options failTestOnZ
#trace (static, tabular)
options tabularReportOnChange
trace (dynamic, tabular)
####################################
# display current environment
####################################
preprocess
simparms
options
trace
modeloptions
####################################
# bus and signal aliases
####################################
vector bist_fail[7:0]
vector cbus_select[1:0]
vector cbus_command[2:0]
vector cycle_type[1:0]
vector color_base[25:0]
vector color_size[1:0]
vector color_format[2:0]
vector z_base[25:0]
vector tex_base[25:0]
vector tex_size[1:0]
vector tex_format[2:0]
vector fillcolor[31:0]
vector blendalpha[7:0]
vector noise[2:0]
vector nextspanxi[19:0]
vector nextspanxf[11:0]
vector nextspancount[11:0]
vector rdpwdepthin[17:0]
vector rdpwredin[7:0]
vector rdpwgreenin[7:0]
vector rdpwbluein[7:0]
vector rdpwalphain[2:0]
vector ccalpha[7:0]
vector rdprred[7:0]
vector rdprgreen[7:0]
vector rdprblue[7:0]
vector rdpralpha[2:0]
vector rdprdepthd[17:0]
vector copy_load[63:0]
vector cbus_data[31:0]
vector dbus_data[63:0]
vector ebus_data[7:0]
equiv load_dv copy_load_oe
equiv cbus_write_enable cbus_data_oe
equiv dma_write_enable dbus_data_oe
equiv dma_write_enable ebus_data_oe
####################################
# assign static inputs
####################################
####################################
# list signals to be dumped in trace file
####################################
#watch clock
#watch gclock
#watch bist_done
#vector bist_fail[7:0]
#watch bist_fail
#watch reset_l
#watch stb_sync_full
#watch freeze_gclk
#watch unfreeze_gclk
#watch grant
#watch start
#watch finish
#watch dma_write_enable
#watch dma_read_enable
#watch cbus_read_enable
#watch cbus_write_enable
#vector cbus_select[1:0]
#watch cbus_select
#vector cbus_command[2:0]
#watch cbus_command
#watch read_grant
#vector cycle_type[1:0]
#watch cycle_type
#watch image_read_en
#watch z_update_en
#watch z_compare_en
#vector color_base[25:0]
#watch color_base
#vector color_size[1:0]
#watch color_size
#vector color_format[2:0]
#watch color_format
#vector z_base[25:0]
#watch z_base
#vector tex_base[25:0]
#watch tex_base
#vector tex_size[1:0]
#watch tex_size
#vector tex_format[2:0]
#watch tex_format
#watch load_tlut_en
#vector fillcolor[31:0]
#watch fillcolor
#watch alphacompen
#watch dithalphaen
#vector blendalpha[7:0]
#watch blendalpha
#vector noise[2:0]
#watch noise
#watch startspant0
#vector nextspanxi[19:0]
#watch nextspanxi
#vector nextspanxf[11:0]
#watch nextspanxf
#vector nextspancount[11:0]
#watch nextspancount
#watch nextspanxdec
#watch load_en
#watch spanbufmt
#vector rdpwdepthin[17:0]
#watch rdpwdepthin
#vector rdpwredin[7:0]
#watch rdpwredin
#vector rdpwgreenin[7:0]
#watch rdpwgreenin
#vector rdpwbluein[7:0]
#watch rdpwbluein
#vector rdpwalphain[2:0]
#watch rdpwalphain
#watch rdpcolorwen
#vector ccalpha[7:0]
#watch ccalpha
#watch dithrgben
#watch load_dv
#watch rdramreq
#watch rdramrw
#watch read_request
#watch stopgclock
#watch start_gclk
#watch rel_sync_full
#watch pipe_busy
#watch spanbufrd
#vector rdprred[7:0]
#watch rdprred
#vector rdprgreen[7:0]
#watch rdprgreen
#vector rdprblue[7:0]
#watch rdprblue
#vector rdpralpha[2:0]
#watch rdpralpha
#vector rdprdepthd[17:0]
#watch rdprdepthd
#watch bist_go
#watch bist_check
#vector copy_load[63:0]
#watch copy_load
#vector cbus_data[31:0]
#watch cbus_data
#vector dbus_data[63:0]
#watch dbus_data
#vector ebus_data[7:0]
#watch ebus_data
####################################
# open trc file
####################################
output (only) [trc]$1
####################################
# load sim file
####################################
load [sim]$1
####################################
# close trc file
####################################
output .
####################################
# display % of nodes toggled
####################################
toggles (totals)
q
q
EOF