tex.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: tex.v,v 1.1.1.1 2002/05/02 03:29:06 blythe Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: tex
// description: Texture Unit
// WARNING: This module is for verification only. Do not
// make any changes to this module and expect them
// to end up in the RCP.
//
// designer: Tony DeLaurier
// date: 8/11/94
//
////////////////////////////////////////////////////////////////////////
`timescale 10ps / 10ps // 1unit = 0.01ns
module tex (gclk, reset_l, bist_go, bist_check, iddq, st_span, ncyc, l, s, t,
w, min_level, detail_en, sharp_en, lod_en, persp_en, copy, samp_type,
tlut_en, tlut_type, max_level, prim_tile, load, shift_coord, tile_adrs,
tile_data, we_tile_size, we_tile_attr, l_frac,
lod_ge_one, s_frac_rg, t_frac_rg, s_frac_ba, t_frac_ba, red_a, green_a,
blue_a, alpha_a, red_b, green_b, blue_b, alpha_b, red_c, green_c, blue_c,
alpha_c, red_d, green_d, blue_d, alpha_d, copy_load, load_dv, bist_done,
bist0_fail, bist1_fail, bist2_fail, bist3_fail, bist4_fail, bist5_fail,
bist6_fail, bist7_fail);
input gclk; // RDP gated clock
input reset_l; // reset (active low)
input bist_go; // mem test enable
input bist_check; // bist test enable
input iddq; // iddq mode enabled
input st_span; // start span
input ncyc; // 0: 1-cycle mode, 1: 2-cycle mode
// pixel data
input [15:0] l; // level of detail
input [15:0] s; // persp. divided texture image coord.
input [15:0] t; // persp. divided texture image coord.
input [15:0] w; // inverse normalized depth
// attribute data
input [4:0] min_level; // minimum lod fraction clamp
input detail_en; // enable detailed texture
input sharp_en; // enable sharpened texture
input lod_en; // use lod in tile indices determination
input persp_en; // enable perspective correction
input copy; // copy mode enabled
input samp_type; // filter enabled
input tlut_en; // enable texture lookup table
input tlut_type; // tlut type
// primitive data
input [2:0] max_level; // number of mipmaps -1 or -2
input [2:0] prim_tile; // base tile index of primitive
input load; // load_tile, load_block or load_tlut
input shift_coord; // treat coord as 12.3 instead of 10.5
// from command interface unit
input [2:0] tile_adrs; // tile write address
input [47:0] tile_data; // tile input data
input we_tile_size; // write enable for tile size data
input we_tile_attr; // write enable for tile attribute data
// to color combine unit
output [8:0] l_frac; // lod fraction for 3rd-axis interpolation
output lod_ge_one; // lod >= 1
// to texture filter unit
output [7:0] s_frac_rg; // s interp fraction to filter (RG)
output [7:0] t_frac_rg; // t interp fraction to filter (RG)
output [7:0] s_frac_ba; // s interp fraction to filter (BA)
output [7:0] t_frac_ba; // t interp fraction to filter (BA)
output [8:0] red_a; // texel a, red / u channel
output [8:0] green_a; // texel a, green / v channel
output [8:0] blue_a; // texel a, blue / y channel
output [8:0] alpha_a; // texel a, alpha / y channel
output [8:0] red_b; // texel b, red / u channel
output [8:0] green_b; // texel b, green / v channel
output [8:0] blue_b; // texel b, blue / y channel
output [8:0] alpha_b; // texel b, alpha / y channel
output [8:0] red_c; // texel c, red / u channel
output [8:0] green_c; // texel c, green / v channel
output [8:0] blue_c; // texel c, blue / y channel
output [8:0] alpha_c; // texel c, alpha / y channel
output [8:0] red_d; // texel d, red / u channel
output [8:0] green_d; // texel d, green / v channel
output [8:0] blue_d; // texel d, blue / y channel
output [8:0] alpha_d; // texel d, alpha / y channel
// to / from memspan unit
inout [63:0] copy_load; // bidirectional copy / load bus
input load_dv; // valid load data on copy_load bus
// other
output bist_done; // bist done
output bist0_fail; // mem test fail flag (active high) (bnk0)
output bist1_fail; // mem test fail flag (active high) (bnk1)
output bist2_fail; // mem test fail flag (active high) (bnk2)
output bist3_fail; // mem test fail flag (active high) (bnk3)
output bist4_fail; // mem test fail flag (active high) (bnk4)
output bist5_fail; // mem test fail flag (active high) (bnk5)
output bist6_fail; // mem test fail flag (active high) (bnk6)
output bist7_fail; // mem test fail flag (active high) (bnk7)
// wires
wire [7:0] adrs_bnk0l; // sorted address to low bank 0
wire [7:0] adrs_bnk1l; // sorted address to low bank 1
wire [7:0] adrs_bnk2l; // sorted address to low bank 2
wire [7:0] adrs_bnk3l; // sorted address to low bank 3
wire [7:0] adrs_bnk0h; // sorted address to high bank 0
wire [7:0] adrs_bnk1h; // sorted address to high bank 1
wire [7:0] adrs_bnk2h; // sorted address to high bank 2
wire [7:0] adrs_bnk3h; // sorted address to high bank 3
wire [4:0] adrs_a; // address of texel a <12,3:0>
wire [4:0] adrs_b_ba; // address of texel b (ba banks) <12,3:0>
wire [4:0] adrs_c; // address of texel c <12,3:0>
wire [4:0] adrs_d_ba; // address of texel d (ba banks) <12,3:0>
wire [4:0] adrs_b_rg; // address of texel b (rg banks) <12,3:0>
wire [4:0] adrs_d_rg; // address of texel d (rg banks) <12,3:0>
wire swap_rg; // swap texels (RG)
wire swap_ba; // swap texels (BA)
wire [2:0] tile_tex_type; // tile_tex_type
wire [1:0] tile_tex_size; // tile_tex_size
wire [3:0] palette; // palette for 4-bit color index
wire odd_t; // odd line
wire a_three; // address a[3] before interleave
wire a_twelve; // address a[12]
wire [7:0] clr_ind_a; // color index texel a
wire [7:0] clr_ind_b; // color index texel b
wire [7:0] clr_ind_c; // color index texel c
wire [7:0] clr_ind_d; // color index texel d
// instance tc
tc tc (.gclk(gclk), .st_span(st_span), .ncyc(ncyc), .l(l), .s(s), .t(t),
.w(w), .min_level(min_level), .detail_en(detail_en),
.sharp_en(sharp_en), .lod_en(lod_en), .persp_en(persp_en),
.copy(copy), .samp_type(samp_type), .tlut_en(tlut_en),
.max_level(max_level), .prim_tile(prim_tile), .load(load),
.shift_coord(shift_coord), .tile_adrs(tile_adrs),
.tile_data(tile_data), .we_tile_size(we_tile_size),
.we_tile_attr(we_tile_attr), .clr_ind_a(clr_ind_a),
.clr_ind_b(clr_ind_b), .clr_ind_c(clr_ind_c), .clr_ind_d(clr_ind_d),
.l_frac(l_frac),
.lod_ge_one(lod_ge_one), .s_frac_rg(s_frac_rg),
.t_frac_rg(t_frac_rg), .s_frac_ba(s_frac_ba), .t_frac_ba(t_frac_ba),
.adrs_bnk0l(adrs_bnk0l), .adrs_bnk1l(adrs_bnk1l),
.adrs_bnk2l(adrs_bnk2l), .adrs_bnk3l(adrs_bnk3l),
.adrs_bnk0h(adrs_bnk0h), .adrs_bnk1h(adrs_bnk1h),
.adrs_bnk2h(adrs_bnk2h), .adrs_bnk3h(adrs_bnk3h), .adrs_a(adrs_a),
.adrs_b_ba(adrs_b_ba), .adrs_c(adrs_c), .adrs_d_ba(adrs_d_ba),
.adrs_b_rg(adrs_b_rg), .adrs_d_rg(adrs_d_rg), .swap_rg(swap_rg),
.swap_ba(swap_ba), .tile_tex_type_1d(tile_tex_type),
.tile_tex_size_1d(tile_tex_size), .palette(palette),
.odd_t(odd_t), .a_three(a_three), .a_twelve(a_twelve));
// instance tm
tm tm (.gclk(gclk), .reset_l(reset_l), .bist_go(bist_go), .bist_check(bist_check),
.iddq(iddq), .tlut_en(tlut_en), .tlut_type(tlut_type),
.adrs_bnk0l(adrs_bnk0l), .adrs_bnk1l(adrs_bnk1l),
.adrs_bnk2l(adrs_bnk2l), .adrs_bnk3l(adrs_bnk3l),
.adrs_bnk0h(adrs_bnk0h), .adrs_bnk1h(adrs_bnk1h),
.adrs_bnk2h(adrs_bnk2h), .adrs_bnk3h(adrs_bnk3h),
.adrs_a(adrs_a), .adrs_b_ba(adrs_b_ba), .adrs_c(adrs_c),
.adrs_d_ba(adrs_d_ba), .adrs_b_rg(adrs_b_rg), .adrs_d_rg(adrs_d_rg),
.swap_rg(swap_rg), .swap_ba(swap_ba), .tile_tex_type(tile_tex_type),
.tile_tex_size(tile_tex_size), .palette(palette), .odd_t(odd_t),
.a_three(a_three), .a_twelve(a_twelve),
.clr_ind_a(clr_ind_a), .clr_ind_b(clr_ind_b),
.clr_ind_c(clr_ind_c), .clr_ind_d(clr_ind_d), .red_a(red_a),
.green_a(green_a), .blue_a(blue_a), .alpha_a(alpha_a), .red_b(red_b),
.green_b(green_b), .blue_b(blue_b), .alpha_b(alpha_b), .red_c(red_c),
.green_c(green_c), .blue_c(blue_c), .alpha_c(alpha_c), .red_d(red_d),
.green_d(green_d), .blue_d(blue_d), .alpha_d(alpha_d),
.copy_load(copy_load), .load_dv(load_dv), .bist_done(bist_done),
.bist0_fail(bist0_fail), .bist1_fail(bist1_fail), .bist2_fail(bist2_fail),
.bist3_fail(bist3_fail), .bist4_fail(bist4_fail), .bist5_fail(bist5_fail),
.bist6_fail(bist6_fail), .bist7_fail(bist7_fail));
endmodule // tex