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/************************************************************************
DMA READ TESTS: File #1
************************************************************************/
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/****************************************************************
DMA TEST #1.36
****************************************************************/
ori $1, $0, 0x0024 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F80
lui $12, 0x2200 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read36: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read36 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk36: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk36 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x7001 /* load random number */
ori $9, $9, 0x6BE2
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.37
****************************************************************/
ori $1, $0, 0x0025 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F88
lui $12, 0x4200 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read37: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read37 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk37: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk37 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x1448 /* load random number */
ori $9, $9, 0x27A5
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.38
****************************************************************/
ori $1, $0, 0x0026 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0F80 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F90
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read38: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read38 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk38: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk38 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x7ECD /* load random number */
ori $9, $9, 0x3A10
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.39
****************************************************************/
ori $1, $0, 0x0027 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0F88 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read39: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read39 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk39: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk39 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x1986 /* load random number */
ori $9, $9, 0x1309
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.40
****************************************************************/
ori $1, $0, 0x0028 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2778
lui $12, 0x0080 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read40: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read40 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk40: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk40 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x0BE6 /* load random number */
ori $9, $9, 0x0688
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.41
****************************************************************/
ori $1, $0, 0x0029 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2780
lui $12, 0x0100 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read41: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read41 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk41: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk41 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x7294 /* load random number */
ori $9, $9, 0x2F45
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.42
****************************************************************/
ori $1, $0, 0x002A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0778 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2788
lui $12, 0x0180 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read42: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read42 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk42: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk42 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x61BD /* load random number */
ori $9, $9, 0x42D0
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.43
****************************************************************/
ori $1, $0, 0x002B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0780 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $12, 0x0200 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read43: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read43 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk43: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk43 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x1250 /* load random number */
ori $9, $9, 0x5EE9
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.44
****************************************************************/
ori $1, $0, 0x002C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0788 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x0280 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read44: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read44 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk44: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk44 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x60FF /* load random number */
ori $9, $9, 0x77A9
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.45
****************************************************************/
ori $1, $0, 0x002D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0x0300 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read45: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read45 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk45: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk45 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x4AD3 /* load random number */
ori $9, $9, 0x13E2
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.46
****************************************************************/
ori $1, $0, 0x002E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0380 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read46: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read46 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk46: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk46 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x05C3 /* load random number */
ori $9, $9, 0x60C3
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.47
****************************************************************/
ori $1, $0, 0x002F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x0400 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read47: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read47 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk47: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk47 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x647F /* load random number */
ori $9, $9, 0x4798
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.48
****************************************************************/
ori $1, $0, 0x0030 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F78
lui $12, 0x0480 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read48: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read48 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk48: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk48 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x1378 /* load random number */
ori $9, $9, 0x0842
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.49
****************************************************************/
ori $1, $0, 0x0031 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F80
lui $12, 0x0500 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read49: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read49 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk49: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk49 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x19CB /* load random number */
ori $9, $9, 0x58C6
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.50
****************************************************************/
ori $1, $0, 0x0032 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0F78 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F88
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read50: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read50 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk50: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk50 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x1391 /* load random number */
ori $9, $9, 0x1DF5
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.51
****************************************************************/
ori $1, $0, 0x0033 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0F80 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read51: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read51 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk51: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk51 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x03CE /* load random number */
ori $9, $9, 0x6B1D
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.52
****************************************************************/
ori $1, $0, 0x0034 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2770
lui $12, 0x0580 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read52: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read52 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk52: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk52 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x12ED /* load random number */
ori $9, $9, 0x0651
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.53
****************************************************************/
ori $1, $0, 0x0035 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2778
lui $12, 0x0600 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read53: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read53 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk53: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk53 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x438C /* load random number */
ori $9, $9, 0x2498
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.54
****************************************************************/
ori $1, $0, 0x0036 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0770 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2780
lui $12, 0x0680 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read54: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read54 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk54: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk54 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x4A08 /* load random number */
ori $9, $9, 0x5D2F
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.55
****************************************************************/
ori $1, $0, 0x0037 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0778 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $12, 0x0700 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read55: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read55 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk55: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk55 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x7404 /* load random number */
ori $9, $9, 0x649D
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.56
****************************************************************/
ori $1, $0, 0x0038 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0780 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x0780 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read56: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read56 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk56: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk56 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x1BE4 /* load random number */
ori $9, $9, 0x684A
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.57
****************************************************************/
ori $1, $0, 0x0039 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0x0800 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read57: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read57 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk57: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk57 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x30F5 /* load random number */
ori $9, $9, 0x50D9
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.58
****************************************************************/
ori $1, $0, 0x003A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0880 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read58: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read58 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk58: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk58 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x17B5 /* load random number */
ori $9, $9, 0x3576
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.59
****************************************************************/
ori $1, $0, 0x003B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x0900 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read59: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read59 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk59: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk59 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x3E74 /* load random number */
ori $9, $9, 0x53D8
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.60
****************************************************************/
ori $1, $0, 0x003C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F70
lui $12, 0x0980 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read60: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read60 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk60: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk60 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x694F /* load random number */
ori $9, $9, 0x60A1
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.61
****************************************************************/
ori $1, $0, 0x003D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F78
lui $12, 0x0A00 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read61: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read61 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk61: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk61 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x1D2F /* load random number */
ori $9, $9, 0x6967
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.62
****************************************************************/
ori $1, $0, 0x003E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0F70 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F80
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read62: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read62 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk62: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk62 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x6450 /* load random number */
ori $9, $9, 0x3D8B
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.63
****************************************************************/
ori $1, $0, 0x003F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0F78 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read63: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read63 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk63: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk63 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x177E /* load random number */
ori $9, $9, 0x54AA
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.64
****************************************************************/
ori $1, $0, 0x0040 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0A80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07F7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read64: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read64 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk64: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk64 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x160D /* load random number */
ori $9, $9, 0x6145
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.65
****************************************************************/
ori $1, $0, 0x0041 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x0B00 /* R12 = READ DMA LEN */
ori $12, $12, 0x07F7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read65: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read65 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk65: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk65 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x132F /* load random number */
ori $9, $9, 0x1BFC
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.66
****************************************************************/
ori $1, $0, 0x0042 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0010 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2810
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07F7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read66: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read66 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk66: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk66 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x0A3D /* load random number */
ori $9, $9, 0x476B
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.67
****************************************************************/
ori $1, $0, 0x0043 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07F7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read67: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read67 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk67: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk67 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x340E /* load random number */
ori $9, $9, 0x6689
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.68
****************************************************************/
ori $1, $0, 0x0044 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07F7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read68: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read68 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk68: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk68 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x2E67 /* load random number */
ori $9, $9, 0x0F20
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.69
****************************************************************/
ori $1, $0, 0x0045 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0C00 /* R12 = READ DMA LEN */
ori $12, $12, 0x07FF
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read69: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read69 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk69: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk69 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x1B36 /* load random number */
ori $9, $9, 0x17AD
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #1.70
****************************************************************/
ori $1, $0, 0x0046 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07FF
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read70: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read70 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk70: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk70 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x000D /* load random number */
ori $9, $9, 0x0BCE
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break