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/************************************************************************
DMA BLOCK READ TESTS: File #2
************************************************************************/
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.word 0x0F8F6B0E
.word 0x755B2AE9
.word 0x26551135
.word 0x54142884
.word 0x74A3626E
.word 0x37DA7F89
.word 0x14652522
.word 0x67EE42E9
.word 0x7E9C3459
.word 0x3CF0496E
.word 0x4BA2081A
.word 0x38097374
.word 0x2C3B6788
.word 0x60DB1067
.word 0x675F20B9
.word 0x162A2000
.word 0x68C96255
.word 0x3D476B3E
.word 0x2C3F12F3
.word 0x7C403127
.word 0x11A04233
.word 0x6AC9633C
.word 0x65AF0F9B
.word 0x65E92DBD
.word 0x2BA22332
.word 0x726447A1
.word 0x736813DF
.word 0x59EC4653
.word 0x48BE577F
.word 0x6F06712E
.word 0x06F018C7
.word 0x23BD50B7
.word 0x1D700EE0
.word 0x5F0A759D
.word 0x111832BC
.word 0x3CFE3371
.word 0x463F6E39
.word 0x25B54B25
.word 0x5F7D20FD
.word 0x66FB4146
.word 0x3D3E170C
.word 0x3CBB5BF9
.word 0x6A094D29
.word 0x742B04B7
.word 0x7F8E1EF3
.word 0x15B909C8
.word 0x50713ABB
.word 0x41B47B81
.word 0x62D97726
.word 0x2BBB213D
.word 0x07B76687
.word 0x60E6421C
.word 0x1AD743F9
.word 0x44B63D7E
.word 0x37A7163F
.word 0x70BD2F3E
.word 0x6ECA245D
.word 0x630D1BAE
.word 0x485C17F2
.word 0x27615F57
.word 0x1F03695C
.word 0x670D5E6D
.word 0x1FBB718A
.word 0x0BA73014
.word 0x7A5D3D9F
.word 0x60734155
.word 0x0EF4004C
.word 0x5E902BDF
.word 0x23C03CEA
.word 0x0FE33C7D
.word 0x7006085A
.word 0x34C7655B
.word 0x079D7B9D
.word 0x187117F8
.word 0x73393432
.word 0x402542EA
/****************************************************************
DMA TEST #2.61
****************************************************************/
ori $1, $0, 0x003D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F78
lui $12, 0x0A00 /* R12 = READ DMA LEN */
ori $12, $12, 0x207F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read61: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read61 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x00A0 /* number of skips */
Chk61: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk61 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done61 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk61 /* go loop */
Done61:
/****************************************************************
DMA TEST #2.62
****************************************************************/
ori $1, $0, 0x003E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0F70 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F80
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read62: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read62 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk62: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk62 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done62 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk62 /* go loop */
Done62:
/****************************************************************
DMA TEST #2.63
****************************************************************/
ori $1, $0, 0x003F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0F78 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read63: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read63 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk63: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk63 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done63 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk63 /* go loop */
Done63:
/****************************************************************
DMA TEST #2.64
****************************************************************/
ori $1, $0, 0x0040 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0A80 /* R12 = READ DMA LEN */
ori $12, $12, 0x17F7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read64: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read64 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00A8 /* number of skips */
Chk64: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk64 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done64 /* exit if zero span */
ori $3, $0, 0x07F8 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk64 /* go loop */
Done64:
/****************************************************************
DMA TEST #2.65
****************************************************************/
ori $1, $0, 0x0041 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x0B00 /* R12 = READ DMA LEN */
ori $12, $12, 0x17F7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read65: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read65 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00B0 /* number of skips */
Chk65: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk65 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done65 /* exit if zero span */
ori $3, $0, 0x07F8 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk65 /* go loop */
Done65:
/****************************************************************
DMA TEST #2.66
****************************************************************/
ori $1, $0, 0x0042 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0010 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2810
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07F7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read66: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read66 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk66: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk66 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done66 /* exit if zero span */
ori $3, $0, 0x07F8 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk66 /* go loop */
Done66:
/****************************************************************
DMA TEST #2.67
****************************************************************/
ori $1, $0, 0x0043 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07F7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read67: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read67 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk67: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk67 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done67 /* exit if zero span */
ori $3, $0, 0x07F8 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk67 /* go loop */
Done67:
/****************************************************************
DMA TEST #2.68
****************************************************************/
ori $1, $0, 0x0044 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07F7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read68: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read68 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk68: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk68 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done68 /* exit if zero span */
ori $3, $0, 0x07F8 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk68 /* go loop */
Done68:
/****************************************************************
DMA TEST #2.69
****************************************************************/
ori $1, $0, 0x0045 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0C00 /* R12 = READ DMA LEN */
ori $12, $12, 0x17FF
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read69: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read69 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00C0 /* number of skips */
Chk69: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk69 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done69 /* exit if zero span */
ori $3, $0, 0x0800 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk69 /* go loop */
Done69:
/****************************************************************
DMA TEST #2.70
****************************************************************/
ori $1, $0, 0x0046 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07FF
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read70: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read70 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk70: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk70 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done70 /* exit if zero span */
ori $3, $0, 0x0800 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk70 /* go loop */
Done70:
/****************************************************************
DMA TEST #2.71
****************************************************************/
ori $1, $0, 0x0047 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07FF
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read71: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read71 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk71: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk71 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done71 /* exit if zero span */
ori $3, $0, 0x0800 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk71 /* go loop */
Done71:
/****************************************************************
DMA TEST #2.72
****************************************************************/
ori $1, $0, 0x0048 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07FF
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read72: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read72 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk72: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk72 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done72 /* exit if zero span */
ori $3, $0, 0x0800 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk72 /* go loop */
Done72:
/****************************************************************
DMA TEST #2.73
****************************************************************/
ori $1, $0, 0x0049 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0807
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read73: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read73 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk73: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk73 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done73 /* exit if zero span */
ori $3, $0, 0x0808 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk73 /* go loop */
Done73:
/****************************************************************
DMA TEST #2.74
****************************************************************/
ori $1, $0, 0x004A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0807
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read74: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read74 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk74: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk74 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done74 /* exit if zero span */
ori $3, $0, 0x0808 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk74 /* go loop */
Done74:
/****************************************************************
DMA TEST #2.75
****************************************************************/
ori $1, $0, 0x004B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0807
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read75: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read75 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk75: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk75 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done75 /* exit if zero span */
ori $3, $0, 0x0808 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk75 /* go loop */
Done75:
/****************************************************************
DMA TEST #2.76
****************************************************************/
ori $1, $0, 0x004C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x080F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read76: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read76 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0810 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk76: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk76 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done76 /* exit if zero span */
ori $3, $0, 0x0810 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk76 /* go loop */
Done76:
/****************************************************************
DMA TEST #2.77
****************************************************************/
ori $1, $0, 0x004D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0FF7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read77: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read77 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0FF8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk77: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk77 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done77 /* exit if zero span */
ori $3, $0, 0x0FF8 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk77 /* go loop */
Done77:
/****************************************************************
DMA TEST #2.78
****************************************************************/
ori $1, $0, 0x004E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0FF7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read78: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read78 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0FF8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk78: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk78 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done78 /* exit if zero span */
ori $3, $0, 0x0FF8 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk78 /* go loop */
Done78:
/****************************************************************
DMA TEST #2.79
****************************************************************/
ori $1, $0, 0x004F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0FFF
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read79: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read79 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x1000 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk79: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk79 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done79 /* exit if zero span */
ori $3, $0, 0x1000 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk79 /* go loop */
Done79:
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break