/****************************************************************
  WHAT:	RSP SCALAR UNIT TEST GENERATOR FOR VECTOR LOAD INSTRUCTIONS
  SCCS: %W% %G%
  FILE:	vld.c
   WHO:	Project Reality - Evan Y. Wang
   (C):	1994 Silicon Graphics, Inc.
 ****************************************************************/
#include <stdio.h>
#include <assert.h>
#include <math.h>
#include "software.h"
#include "gen.h"
#include "suregre.h"

/****************************************************************
  DISCLAIMER: This test is tacked on to suregre at the end.  It
  does not comply with the suregre structure in that the tests
  are not automatically broken into smaller pieces.  So when
  assembling these test, watch for the warning messages about
  the number of instructions exceeding IMEM size!
 ****************************************************************/

PRIVATE UD32 DMem[0x1000>>2];

PRIVATE u32 Rand32()
{
    return (((u32) (rand()&0x3FF)<<22)
	    | ((u32) (rand()&0x3FF)<<12)
	    | ((u32) (rand()&0xFFF)));
}

/************************************************************************
  DmemInit(..) - initialize DMEM.
 ************************************************************************/
PRIVATE void DMemInit(outp,itype)
    FILE *outp;
    int itype;
{
    int i = 0;
    u32 tdp;

    tdp = 0;
    switch (itype) {
      case VLD_TRNS:
	for (i=0; i<4*8; i++, tdp+=4)
	    fprintf(outp,"\t.word\t0x%8.8lX\t\t/* Addr: 0x%4.4X */\n",
		    DMem[i].w=0, tdp);
	break;
      case VST_WRAP:
      case VST_TRNS:
	for (i=0; i<4*8; i++, tdp+=4)
	    fprintf(outp,"\t.word\t0x%8.8lX\t\t/* Addr: 0x%4.4X */\n",
		    DMem[i].w=0x00010002+0x00020002*i, tdp);
	break;
    }
    for (; i<(DMEM_SIZE>>2); i++, tdp+=4)
        fprintf(outp,"\t.word\t0x%8.8lX\t\t/* Addr: 0x%4.4X */\n",
                DMem[i].w=Rand32(), tdp);
}   /* DMemInit */

PRIVATE void GenCase(outp,tno,itype,vT,el,vR,vD,rA,rAval,rB,rR)
    FILE *outp;		/* output file		*/
    int tno;		/* test number		*/
    int itype;		/* instruction type	*/
    int vT;		/* target of test	*/
    int el;		/* element		*/
    int vR;		/* result check		*/
    int vD;		/* dump			*/
    int rA;		/* SU addr reg		*/
    u32 rAval;		/* starting data addr	*/
    int rB;		/* temp			*/
    int rR;		/* VNE result		*/
{
    int i;

    fprintf(outp,"\n\t/* TEST #%2.2d ",tno);
    fprintf(outp,"*********************************************/\n");

    fprintf(outp,"\tori\t$1,\t$0,\t%d\n",tno);
    switch (itype) {
      case VLD_TRNS:
      case VST_TRNS:
	for (i=0; i<8; i++)
	    fprintf(outp,"\tlqv\t$v%d,\t0x%X($%d)\n",vR+i,(0x10*i),rA);
	/* intentional fall-thru */
      case VST_WRAP:
	for (i=0; i<8; i++)
	    fprintf(outp,"\tlqv\t$v%d,\t0x%X($%d)\n",vT+i,(0x10*i),rA);
	break;
    }

    fprintf(outp,"\taddi\t$%d,\t$%d,\t0x80\n",rA,rA);

    switch (itype) {
      case VLD_TRNS:
	for (i=0; i<8; i++)
	    fprintf(outp,"\tlsv\t$v%d[%d],\t0x%X($%d)\n",
		    vR+i,(16-el+2*i)&0xE,2*i,rA);
	fprintf(outp,"\n\tnop\n\tnop\n\tnop\n");
	fprintf(outp,"\tltv\t$v%d[%d],\t0($%d)\n",vT,el,rA);
	fprintf(outp,"\tnop\n\tnop\n\tnop\n\n");
	break;
      case VST_TRNS:
	for (i=0; i<8; i++)
	    fprintf(outp,"\tlsv\t$v%d[%d],\t0x%X($%d)\n",
		    vR+i,(16-el+2*i)&0xE,(16-el+2*i)&0xE,rA);
	fprintf(outp,"\n\tnop\n\tnop\n\tnop\n");
	fprintf(outp,"\tstv\t$v%d[%d],\t0($%d)\n",vT,el,rA);
	fprintf(outp,"\tnop\n\tnop\n\tnop\n\n");
	for (i=0; i<8; i++)
	    fprintf(outp,"\tlsv\t$v%d[%d],\t0x%X($%d)\n",
		    vR+i,(16-el+2*i)&0xE,(16-el+2*i)&0xE,rA);

	break;
      case VST_WRAP:
	for (i=0; i<8; i++) {
	    fprintf(outp,"\n");
	    fprintf(outp,"\tswv\t$v%d[%d],\t0($%d)\n",vT+i,(el+2*i)&0xE,rA);
	    fprintf(outp,"\tnop\n\n");
	    fprintf(outp,"\taddi\t$%d,\t$%d,\t0x%X\n",rR,rA,(16-el-2*i)&0xE);
	    fprintf(outp,"\tlqv\t$v%d[0],\t0($%d)\n",vR+i,rR);
	    fprintf(outp,"\tlrv\t$v%d[0],\t0($%d)\n",vR+i,rR);
	}
	break;
    }

    for (i=0; i<8; i++) {
	fprintf(outp,"\tctc2\t$0,\t$v0\n");	/* clear VCO */
	fprintf(outp,"\tveq\t$v%d,\t$v%d,\t$v%d\n",vD,vT+i,vR+i);
	fprintf(outp,"\tcfc2\t$%d,\t$v1\n",rR);	/* fetch VCC */
	fprintf(outp,"\tbne\t$%d,\t$%d,\tFail\n",rB,rR);
    }

}   /* GenCase */

int VtwGen(outp, ip)
    FILE *outp;
    I_TABLE *ip;
{
    int i;
    int vT = 0;
    int vR = 8;
    int vD = 31;

    El = 0;
    DMemInit(outp,ip->vec);

    OpA = DMEM_BASE;
    fprintf(outp,"\tlui\t$%d,\t0x%4.4X\n",rA,OpA>>16);
    fprintf(outp,"\tori\t$%d,\t0x%4.4X\n",rA,OpA&0xFFFF);
    OpB = 0xFF;
    fprintf(outp,"\tlui\t$%d,\t0\n",rB);
    fprintf(outp,"\tori\t$%d,\t$%d,\t0xFF\n",rB,rB);

    /************************************************************
      For our first test, we make it the same as the example
      given in the MME sketch in Sec.5*7*3.
     ************************************************************/
    switch (ip->vec) {
      case VLD_TRNS:
	El = 0x6;
	GenCase(outp,CurTcNo,ip->vec,vT,El,vR,vD,rA,OpA,rB,rR);
	CurTcNo++;
	break;
      case VST_TRNS:
	El = 0xA;
	GenCase(outp,CurTcNo,ip->vec,vT,El,vR,vD,rA,OpA,rB,rR);
	CurTcNo++;
	break;
      case VST_WRAP:
	fprintf(outp,"\tlqv\t$v%d,\t0 ($%d)\n",0,rA);
	for (i=8; i<32; i++)
	    fprintf(outp,"\tvnxor\t$v%d,\t$v%d,\t$v%d\n",i,0,0);
	/* there is no example given in MME sketch for SW */
	break;
    }

    /************************************************************
      For the rest of our tests, go through all element values,
      use random data, and use all VU registers.
     ************************************************************/
    for (i=1,El=0; El<16; i=(i+1)&3,El+=2) {
	vT = i<<3;
	vR = (vT+8)&0x1F;
	vD = (vT-1)&0x1F;
	GenCase(outp,CurTcNo,ip->vec,vT,El,vR,vD,rA,OpA,rB,rR);
	CurTcNo++;
    }

    return 0;

}   /* VtwGen */