`timescale 1ns / 10ps

`include "rsp_regr.h"

module rsp_random_dma;


/***********************************************************
 * Random IMEM DMA
 ***********************************************************/

reg [3:0] halt_len;
reg [1:0] halt_wait;
reg dmem_dma_with_halt;

reg dmem_dma_X;
reg imem_dma_X;
reg mem_write_X;

reg dma_len_eq1;
reg dma_len_eq1_X;
reg dma_len_eq1_d1;
reg dma_len_eq1_d2;
reg dma_len_eq1_d3;
reg dma_len_eq1_d4;

reg imem_dma_d1;
reg imem_dma_d2;
reg imem_dma_d3;
reg imem_dma_d4;
reg imem_dma_d5;
reg imem_dma_d6;
reg imem_dma_d7;
reg imem_dma_d8;
reg imem_dma_d9;
reg imem_dma_d10;

reg dmem_dma_d1;
reg dmem_dma_d2;
reg dmem_dma_d3;
reg dmem_dma_d4;

reg mem_write_d1;
reg mem_write_d2;
reg mem_write_d3;
reg mem_write_d4;

reg [3:0] dma_len;
reg [8:0] dma_addr;
reg [8:0] dma_addr_d1;

reg [7:0] dmem_addr_d2;
reg [7:0] dmem_addr_d3;
reg [7:0] dmem_addr_d4;

reg [3:0] dma_wait;
reg [5:0] dma_cnt;
reg [63:0] dma_data;
reg [63:0] dma_dataH;
reg [63:0] dma_dataH_d1;
reg [63:0] dma_dataH_d2;
reg [63:0] dma_dataH_d3;
reg [63:0] dma_dataH_d4;
reg [63:0] dma_dataL;
reg [63:0] dma_dataL_d1;
reg [63:0] dma_dataL_d2;
reg [63:0] dma_dataL_d3;
reg [63:0] dma_dataL_d4;
reg [31:0] random_num;

reg [63:0] dmem_dataH;
reg [63:0] dmem_dataL;

reg random_dma_on;
reg random_idma_mode;
reg random_ddma_mode;
reg dma_cycle;
reg dma_ip;
reg dma_ip_d1;
reg dma_ip_d2;
reg dma_ip_d3;
reg dma_ip_d4;
reg in_the_loop;
reg [31:0] seed;
reg [31:0] fp;
reg imem_dma;
reg dmem_dma;
reg mem_write;
reg dmem_addr_conflict;

reg [255:0] dmem_wr_flag;

reg halt;
reg halt_ip;
reg halt_ip_d1;
reg halt_ip_d2;
reg halt_ip_d3;
reg halt_ip_d4;
reg halt_ip_d5;
reg halt_ip_d6;
reg halt_ip_d7;
reg halt_ip_d8;

reg random_halt_mode;

integer i,j,k;

wire [9:0] imem_dma_d_vector;
reg halt_not_allowed;

initial
begin
  halt_not_allowed = 0;
  dma_cycle = 0;
  random_dma_on = 0;
  random_idma_mode = 0;
  random_ddma_mode = 0;
  halt = 0;
  halt_ip = 0;
  halt_ip_d1 = 0;
  halt_ip_d2 = 0;
  halt_ip_d3 = 0;
  halt_ip_d4 = 0;
  halt_ip_d5 = 0;
  halt_ip_d6 = 0;
  halt_ip_d7 = 0;
  halt_ip_d8 = 0;
  imem_dma_d1 = 0;
  imem_dma_d2 = 0;
  imem_dma_d3 = 0;
  imem_dma_d4 = 0;
  imem_dma_d5 = 0;
  imem_dma_d6 = 0;
  imem_dma_d7 = 0;
  imem_dma_d8 = 0;
  imem_dma_d9 = 0;
  imem_dma_d10= 0;
  random_halt_mode = 0;
  dma_len = 0;
  dma_addr = 0;
  dma_addr_d1 = 0;
  dma_wait = 0;
  dma_cnt = 0;
  dma_dataH = 0;
  dma_dataL = 0;
  random_num = 0;
  in_the_loop = 0;
  imem_dma = 0;
  dmem_dma = 0;
  mem_write = 0;

  dma_ip = 0;
  dma_ip_d1 = 0;
  dma_ip_d2 = 0;
  dma_ip_d3 = 0;
  dma_ip_d4 = 0;

  dmem_wr_flag = 'h0;

  dmem_addr_conflict = 0;

end


always @(posedge random_dma_on)
begin

 $display(" Starting random_dma with seed=%d",seed);
 $fwrite(fp," Starting random_dma with seed=%d\n",seed);

 random_num = seed;

 @(posedge `CLK);
 while (random_dma_on)
  begin
    in_the_loop = 1;

    random_num = $random(random_num);

    dma_len = {1'b0,random_num[2:0]}&4'h5;
    halt_len ={1'b0,random_num[9:7]}&4'h5;
    halt_wait = {random_num[11],1'b0};
    dma_wait = {2'b0,random_num[16:15]};
    if (dma_len=='h0) dma_len = 'h1;

    dma_len_eq1 = (dma_len=='h1);
   
    dmem_dma  = random_ddma_mode && ((random_num[31]&&random_num[12]) ||
				     (!random_idma_mode&&!random_halt_mode)
				    );
    halt = random_halt_mode && !dmem_dma && ((random_num[30]&&random_num[15]) ||
                                             (!random_idma_mode&&!random_ddma_mode)
                                            ) ;
    dmem_dma_with_halt = random_ddma_mode && random_halt_mode && halt && random_num[18] && 
			!imem_dma_d1 && !imem_dma_d2; 

    if (!random_idma_mode && !dmem_dma && !halt) dmem_dma = 1;

    if (dmem_dma_with_halt) 
      begin
	dmem_dma = 1;
	halt = 1;
      end
  
    if (halt_not_allowed && halt)
       begin
	 dmem_dma = 1;
         dmem_dma_with_halt = 0;
	 @(posedge `CLK);
	 @(posedge `CLK);
       end
 
    imem_dma  = !halt && !dmem_dma;
    mem_write = imem_dma || random_num[5];

    dmem_dma_X <= dmem_dma;
    imem_dma_X <= imem_dma;
    mem_write_X <= mem_write;
    dma_len_eq1_X <= dma_len_eq1;


    for (dma_cnt = 0; dma_cnt<dma_wait; dma_cnt = dma_cnt+1) @(posedge `CLK);
    
    
    if (halt || imem_dma) wait( !halt_ip_d1 && 
			        !halt_ip_d2 && 
			        !halt_ip_d3 && 
			        !halt_ip_d4 && 
			       (!halt_ip_d5 || imem_dma) && 
			       (!halt_ip_d6 || imem_dma) && 
			       (!halt_ip_d7 || imem_dma) && 
			       (!halt_ip_d8 || imem_dma) &&  !imem_dma_d1 &&
			   		      		     !imem_dma_d2 &&
			   		      		     !imem_dma_d3 &&
			   		      		    (!imem_dma_d4 || imem_dma) &&
			   		      		    (!imem_dma_d5 || imem_dma) &&
			   		      		    (!imem_dma_d6 || imem_dma) &&
			   		      		    (!imem_dma_d7 || imem_dma)
			      );

    $fwrite(fp,"\n");
    $fwrite(fp,"time=%d, %s: ",$time, (dmem_dma_with_halt) ? "DMEM_DMA_with_Halt_Cycle_Starts" :
				      (halt)     	   ? "Halt_Cycle_Starts" :
                                      (imem_dma) 	   ? "IMEM_DMA_Starts"   :
                                                   	     "DMEM_DMA_Starts"   );
    if (halt && !dmem_dma_with_halt) $fwrite(fp,"\n"); 

    if (!halt || dmem_dma_with_halt)
      begin
         $fwrite(fp,"dma_dir=%s, dma_wait=%d, dma_len=%d\n",
				(mem_write) ? "WR" : "RD", dma_wait,dma_len);
         if (dmem_dma_with_halt)
           fork
	    dma_driver;
	    halt_driver(1'b1);
	   join
         else
	    dma_driver;
       end
    else
       halt_driver(1'b1);

    $fwrite(fp,"time=%d, %s: \n",$time, (dmem_dma_with_halt) ? "DMEM_DMA_with_Halt_Cycle_End" :
					(halt)     	     ? "Halt_Cycle_Ends" :
                                        (imem_dma) 	     ? "IMEM_DMA_Ends" :
                                                     	       "DMEM_DMA_Ends");
    $fwrite(fp,"\n");

    if (!random_dma_on)
      begin
        if (!halt) @(negedge dma_cycle);
        in_the_loop = 0;
        @(posedge `CLK);
      end

  end

  seed = random_num;

end

assign imem_dma_d_vector[9:0] = {imem_dma_d10,imem_dma_d9,imem_dma_d8,imem_dma_d7,imem_dma_d6,
        			 imem_dma_d5, imem_dma_d4,imem_dma_d3,imem_dma_d2,imem_dma_d1
				};
always @(posedge `CLK)
    if (imem_dma_d_vector !== 0 && dmem_dma_X && dma_ip)
	halt_not_allowed <= 1;
    else
    if (imem_dma_d_vector !== 0)
	halt_not_allowed <= 0;
	 

always @(posedge `CLK) halt_ip_d1 <= halt_ip;
always @(posedge `CLK) halt_ip_d2 <= halt_ip_d1;
always @(posedge `CLK) halt_ip_d3 <= halt_ip_d2;
always @(posedge `CLK) halt_ip_d4 <= halt_ip_d3;
always @(posedge `CLK) halt_ip_d5 <= halt_ip_d4;
always @(posedge `CLK) halt_ip_d6 <= halt_ip_d5;
always @(posedge `CLK) halt_ip_d7 <= halt_ip_d6;
always @(posedge `CLK) halt_ip_d8 <= halt_ip_d7;

always @(posedge `CLK) dma_len_eq1_d1 <= dma_len_eq1_X && dma_ip;
always @(posedge `CLK) dma_len_eq1_d2 <= dma_len_eq1_d1;
always @(posedge `CLK) dma_len_eq1_d3 <= dma_len_eq1_d2;
always @(posedge `CLK) dma_len_eq1_d4 <= dma_len_eq1_d3;

always @(posedge `CLK) dmem_dma_d1 <= dmem_dma_X && dma_ip;
always @(posedge `CLK) dmem_dma_d2 <= dmem_dma_d1;
always @(posedge `CLK) dmem_dma_d3 <= dmem_dma_d2;
always @(posedge `CLK) dmem_dma_d4 <= dmem_dma_d3;

always @(posedge `CLK) imem_dma_d1 <= imem_dma_X && dma_ip;
always @(posedge `CLK) imem_dma_d2 <= imem_dma_d1;
always @(posedge `CLK) imem_dma_d3 <= imem_dma_d2;
always @(posedge `CLK) imem_dma_d4 <= imem_dma_d3;
always @(posedge `CLK) imem_dma_d5 <= imem_dma_d4;
always @(posedge `CLK) imem_dma_d6 <= imem_dma_d5;
always @(posedge `CLK) imem_dma_d7 <= imem_dma_d6;
always @(posedge `CLK) imem_dma_d8 <= imem_dma_d7;
always @(posedge `CLK) imem_dma_d9 <= imem_dma_d8;
always @(posedge `CLK) imem_dma_d10<= imem_dma_d9;

always @(posedge `CLK) mem_write_d1 <= mem_write_X && dma_ip;
always @(posedge `CLK) mem_write_d2 <= mem_write_d1;
always @(posedge `CLK) mem_write_d3 <= mem_write_d2;
always @(posedge `CLK) mem_write_d4 <= mem_write_d3;

always @(posedge `CLK) dma_ip_d1 <= dma_ip;
always @(posedge `CLK) dma_ip_d2 <= dma_ip_d1 && dmem_dma_d1;
always @(posedge `CLK) dma_ip_d3 <= dma_ip_d2;
always @(posedge `CLK) dma_ip_d4 <= dma_ip_d3;

always @(posedge `CLK) dma_cycle <= (dma_ip || (dma_ip_d1 && dmem_dma_d1) || dma_ip_d2 || dma_ip_d3);

always @(posedge `CLK) dma_addr_d1 <= dma_addr;

always @(posedge `CLK) dmem_addr_d2 <= (dma_addr_d1>>1);
always @(posedge `CLK) dmem_addr_d3 <= dmem_addr_d2;
always @(posedge `CLK) dmem_addr_d4 <= dmem_addr_d3;

always @(posedge `CLK) dma_dataH_d1 <= dma_dataH;
always @(posedge `CLK) dma_dataH_d2 <= dma_dataH_d1;
always @(posedge `CLK) dma_dataH_d3 <= dma_dataH_d2;
always @(posedge `CLK) dma_dataH_d4 <= dma_dataH_d3;

always @(posedge `CLK) dma_dataL_d1 <= dma_dataL;
always @(posedge `CLK) dma_dataL_d2 <= dma_dataL_d1;
always @(posedge `CLK) dma_dataL_d3 <= dma_dataL_d2;
always @(posedge `CLK) dma_dataL_d4 <= dma_dataL_d3;


always @(negedge `CLK)
begin
    if (dma_ip) 
	begin 
	  dma_addr = (random_num >> dma_cnt) & 9'h1ff; 
	  dma_dataH = `IMEM[dma_addr]; 
          if (dmem_dma) 
	     begin 
		dma_addr = dma_addr>>1; 
		dmem_addr_conflict = dmem_wr_flag[dma_addr]; 
		i = 0; 
		while (dmem_addr_conflict && i<256) 
		  begin
	            i = i+1;
                    dmem_addr_conflict = dmem_wr_flag[(dma_addr+i)&8'hff];
                  end

		dma_addr = (dma_addr+i)&8'hff; 

                dma_dataH[63:56] = `DMEM15[dma_addr]; 
                dma_dataH[55:48] = `DMEM14[dma_addr]; 
                dma_dataH[47:40] = `DMEM13[dma_addr]; 
                dma_dataH[39:32] = `DMEM12[dma_addr]; 
                dma_dataH[31:24] = `DMEM11[dma_addr]; 
                dma_dataH[23:16] = `DMEM10[dma_addr]; 
                dma_dataH[15:8]  = `DMEM9[dma_addr]; 
                dma_dataH[7:0]   = `DMEM8[dma_addr]; 

                dma_dataL[63:56] = `DMEM7[dma_addr]; 
                dma_dataL[55:48] = `DMEM6[dma_addr]; 
                dma_dataL[47:40] = `DMEM5[dma_addr]; 
                dma_dataL[39:32] = `DMEM4[dma_addr]; 
                dma_dataL[31:24] = `DMEM3[dma_addr]; 
                dma_dataL[23:16] = `DMEM2[dma_addr]; 
                dma_dataL[15:8]  = `DMEM1[dma_addr]; 
                dma_dataL[7:0]   = `DMEM0[dma_addr]; 

	        dma_addr = dma_addr<<1;
             end

          if (dmem_dma)
           $fwrite(fp,"time=%d, dmem_addr = %h, dma_data = %h_%h,\n",
		      $time,    (dma_addr>>1),       dma_dataH,dma_dataL);
          else
           $fwrite(fp,"time=%d, imem_addr = %h, dma_data = %h \n",
		      $time,    dma_addr,       dma_dataH);

          force `rsp_path.dma_imem_select = imem_dma;
  	  force `rsp_path.dma_rd_to_dm = mem_write;
  	  force `rsp_path.dma_dm_to_rd = !mem_write;
        end
    else
        begin
         release `rsp_path.dma_imem_select;
         release `rsp_path.dma_rd_to_dm;
         release `rsp_path.dma_dm_to_rd;
        end

    if (dma_ip_d1)
      begin
         force `rsp_path.dma_address = dma_addr_d1;
         if (mem_write_d1&&dmem_dma_d1)
		force `rsp_path.dma_wen = 4'hF;
      end
    else
      begin
         release `rsp_path.dma_address;
         release `rsp_path.dma_wen;
      end

    if ((dma_ip&&mem_write) || (dma_ip_d1&&mem_write_d1&&dmem_dma_d1))
       begin

         if (dma_ip) 
            dma_data = dma_dataH;
         else
            dma_data = dma_dataL_d1;

         force `rsp_path.mem_write_data = dma_data;

       end
    else
         release `rsp_path.mem_write_data;

    if (dma_ip_d3) 
      begin 
         dmem_dataH = `rsp_path.dmem_rd_data;
         if (mem_write_d3)
           begin
             dmem_dataH[63:56] = `DMEM15[dmem_addr_d3];
             dmem_dataH[55:48] = `DMEM14[dmem_addr_d3];
             dmem_dataH[47:40] = `DMEM13[dmem_addr_d3];
             dmem_dataH[39:32] = `DMEM12[dmem_addr_d3];
             dmem_dataH[31:24] = `DMEM11[dmem_addr_d3];
             dmem_dataH[23:16] = `DMEM10[dmem_addr_d3];
             dmem_dataH[15:8]  = `DMEM9[dmem_addr_d3];
             dmem_dataH[7:0]   = `DMEM8[dmem_addr_d3];
             dmem_dataL[63:56] = `DMEM7[dmem_addr_d3];
             dmem_dataL[55:48] = `DMEM6[dmem_addr_d3];
             dmem_dataL[47:40] = `DMEM5[dmem_addr_d3];
             dmem_dataL[39:32] = `DMEM4[dmem_addr_d3];
             dmem_dataL[31:24] = `DMEM3[dmem_addr_d3];
             dmem_dataL[23:16] = `DMEM2[dmem_addr_d3];
             dmem_dataL[15:8]  = `DMEM1[dmem_addr_d3];
             dmem_dataL[7:0]   = `DMEM0[dmem_addr_d3];

             if ({dmem_dataH,dmem_dataL} !== {dma_dataH_d3,dma_dataL_d3})
               $display($time, "  ERROR:dmem_dma_write(16 Bytes): dmem data missmatch, Addr: %h, Expected Data = %h, Actual Data = %h",
								dmem_addr_d3,{dma_dataH_d3,dma_dataL_d3},{dmem_dataH,dmem_dataL});
           end
      end 

    if (dma_ip_d4) 
      begin 
       dmem_dataL = `rsp_path.dmem_rd_data;

       if (!mem_write_d4 && !dma_len_eq1_d4)
         if ({dmem_dataH,dmem_dataL} !== {dma_dataH_d4,dma_dataL_d4})
               $display($time, "  ERROR:dmem_dma_read(16 Bytes): dmem data missmatch, Addr: %h, Expected Data = %h, Actual Data = %h",
								dmem_addr_d4,{dma_dataH_d4,dma_dataL_d4},{dmem_dataH,dmem_dataL});
       else
       if (!mem_write_d4 && dma_len_eq1_d4)
         if (dmem_dataH !== dma_dataH_d4)
               $display($time, "  ERROR:dmem_dma_read(8 Bytes): dmem data missmatch, Addr: %h, Expected Data = %h, Actual Data = %h",
								dmem_addr_d4,dma_dataH_d4,dmem_dataH);
      end


end

task dma_driver; 
begin

  for (dma_cnt= 0; dma_cnt<dma_len; dma_cnt = dma_cnt+1)  
    begin
       begin
          dma_ip <= 1; 
          @(posedge `CLK);
       end
      if (dmem_dma && (mem_write || !dma_len_eq1))
         begin
             dma_ip <= 0; 
             @(posedge `CLK); 
         end
    end

  dma_ip <= 0; 

end
endtask

task halt_driver;
input extra_wait;
integer i;	     
begin
   halt_len = halt_len+4;
   halt_ip <= 1;
   if (extra_wait) for (i= 0; i<halt_wait; i = i+1) @(posedge `CLK);
   @(negedge `CLK) force `rsp_path.halt = 1;
   for (i= 0; i<halt_len; i = i+1) @(posedge `CLK);
   @(negedge `CLK) release `rsp_path.halt;
   halt_ip <= 0;
   @(posedge `CLK);
end
endtask

endmodule